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specification subject to change without notice, as is and for reference only. for purchasing, please contact sales representatives. it8 7 80f s erverwork i/o (c o d e n a m e : s w i o ) p r e l im i nary specif i ca t i on v 0 . 3 integrated technology express, inc.
c o p y rig h t ? 2 003 i t e, i n c . this is preliminary document release. all specifications are subject to change without notice. the material contained in this document supersedes all previous documentation issued for the related products included herein. please contact ite, inc. for the latest document(s). all sales are subject to ite?s standard terms and conditions, a copy of which is included in the back of this document. ite, IT8780F is a trademark of ite, inc. all other trademarks are claimed by their respective owners. all specifications are subject to change without notice. additional copies of this manual or other ite literature may be obtained from: ite, inc. phone: (02) 29126889 marketing department fax: (02) 2910-2551, 2910-2552 8f, no. 233-1, bao chiao rd., hsin tien, taipei county 231, taiwan, r.o.c. ite (usa) inc. phone: (408) 530-8860 marketing department fax: (408) 530-8861 1235 midas way sunnyvale, ca 94086 u.s.a. ite (usa) inc. phone: (512) 388-7880 eastern u.s.a. sales office fax: (512) 388-3108 896 summit st., #105 round rock, tx 78664 u.s.a. if you have any marketing or sales questions, please contact: lawrence liu, at ite taiwan: e-mail: lawrence.liu@ite.com.tw , tel: 886-2-26579896 x6071, fax: 886-2-26578561 david lin , at ite u.s.a: e-mail: david.lin@iteusa.com , tel: (408) 530-8860 x238, fax: (408) 530-8861 don gardenhire , at ite eastern usa office: e-mail: don.gardenhire@iteusa.com tel: (512) 388-7880, fax: (512) 388-3108 to find out more about ite, visit our world wide web at: http://www.ite.com.tw http://www.iteusa.com or e-mail itesupport@ite.com.tw for more product information/services.
contents 1. features ....................................................................................................................... ............................1 2. general description ............................................................................................................ ......................3 3. block diagram .................................................................................................................. ........................5 4. pin configuration .............................................................................................................. ........................7 5. IT8780F pin descriptions....................................................................................................... .................11 6. list of gpio pins .............................................................................................................. ......................21 7. power on strapping options ..................................................................................................... .............23 8. configuration .................................................................................................................. ........................25 8.1 configuring sequence description............................................................................................... .25 8.2 description of the configuration registers ....................................................................................2 6 8.3 global configuration registers (ldn: all) .....................................................................................3 2 8.3.1 configure control (index=02h) .........................................................................................32 8.3.2 logical device number (ldn, index=07h)........................................................................32 8.3.3 chip id byte 1 (index=20h, default=87h) .........................................................................32 8.3.4 chip id byte 2 (index=21h, default=80h) .........................................................................32 8.3.5 chip version (index=22h, default=00h) ............................................................................32 8.3.6 clock selection and flash rom i/f control register (index=23h, default=ss0000s0b, vsb) .............................................................................................................................. .....33 8.3.7 function fast disable register (index=24h, default=s1000000b, vsb) ............................34 8.3.8 gpio set 4 multi-function pin selection register (index=25h, default=03h, vsb) ...........35 8.3.9 gpio set 5 multi-function pin selection register (index=26h, default= 01100s00b, vsb)36 8.3.10 gpio set 6 and misc. multi-function pin selection register (index=27h, default= s00000ssb, vsb) .............................................................................................................37 8.3.11 reserved registers (index=2ah, 2bh and 2ch, default=00h, --, --) ..................................38 8.3.12 test 1 register (index=2eh, default=00h) ........................................................................38 8.3.13 test 2 register (index=2fh, default=00h) ........................................................................38 8.4 fdc configuration registers (ldn=00h) ......................................................................................38 8.4.1 fdc activate (index=30h, default=00h) ...........................................................................38 8.4.2 fdc base address msb register (index=60h, default=03h)............................................38 8.4.3 fdc base address lsb register (index=61h, default=f0h) ............................................38 8.4.4 fdc interrupt level select (index=70h, default=06h) .......................................................38 8.4.5 fdc dma channel select (index=74h, default=02h) .......................................................38 8.4.6 fdc special configuration register 1 (index=f0h, d7efault=00h)....................................39 8.4.7 fdc special configuration register 2 (index=f1h, default=00h)......................................39 8.5 serial port 1 configuration registers (ldn=01h) ..........................................................................39 8.5.1 serial port 1 activate (index=30h, default=00h) ...............................................................39 8.5.2 serial port 1 base address msb register (index=60h, default=03h) .................................39 8.5.3 serial port 1 base address lsb register (index=61h, default=f8h) .................................. 40 8.5.4 serial port 1 interrupt level select (index=70h, default=04h) ...........................................40 8.5.5 serial port 1 special configuration register (index=f0h, default=00h).............................40 8.6 serial port 2 configuration registers (ldn=02h) ..........................................................................40 8.6.1 serial port 2 activate (index=30h, default=00h) ...............................................................40 8.6.2 serial port 2 base address msb register (index=60h, default=02h) .................................40 8.6.3 serial port 2 base address lsb register (index=61h, default=f8h) .................................. 40 8.6.4 serial port 2 interrupt level select (index=70h, default=03h) ...........................................41 8.6.5 serial port 2 special configuration register 1 (index=f0h, default=00h)..........................41 8.6.6 serial port 2 special configuration register 2 (index=f1h, default=00h)..........................41 8.6.7 serial port 2 special configuration register 3 (index=f2h, default=7fh)..........................41 8.7 parallel port configuration registers (ldn=03h) ..........................................................................42 8.7.1 parallel port activate (index=30h, default=00h)................................................................42 8.7.2 parallel port primary base address msb register (index=60h, default=03h)..................... 42 8.7.3 parallel port primary base address lsb register (index=61h, default=78h) ....................42
www.ite.com.tw IT8780F v0.3 iii contents 8.7.4 parallel port secondary base address msb register (index=62h, default=07h) ................ 42 8.7.5 parallel port secondary base address lsb register (index=63h, default=78h) ...............42 8.7.6 post data port base address msb register (index=64h, default=00h) ...........................42 8.7.7 post data port base address lsb register (index=65h, default=80h)...........................42 8.7.8 parallel port interrupt level select (index =70h, default=07h) ..........................................43 8.7.9 parallel port dma channel select (index=74h, default=03h)............................................43 8.7.10 parallel port special configuration register (index=f0h, default=03h) .............................43 8.8 swc and acpi configuration registers (ldn=04h) .....................................................................43 8.8.1 swc activate register (index=30h, default=00h).............................................................43 8.8.2 pm1b_evt_blk base address msb register (index=60h, default=00h) ..........................43 8.8.3 pm1b_evt_blk base address lsb register (index=61h, default=00h) ...........................44 8.8.4 pm1b_cnt_blk base address msb register (index=62h, default=00h) .......................... 44 8.8.5 pm1b_cnt_blk base address lsb register (index=63h, default=00h) ........................... 44 8.8.6 gpe1_blk base address msb register (index=64h, default=00h)................................... 44 8.8.7 gpe1_blk base address lsb register (index=65h, default=00h)....................................44 8.8.8 swc interrupt level select (index=70h, default=00h) ......................................................44 8.8.9 gpe1_sts_0 to irq enable register (ge0_2irq) (index=e0h, default=00h).................44 8.8.10 gpe1_sts_1 to irq enable register (ge1_2irq) (index=e1h, default=00h).................45 8.8.11 gpe1_sts_2 to irq enable register (ge2_2irq) (index=e2h, default=00h).................45 8.8.12 gpe1_sts_3 to irq enable register (ge3_2irq) (index=e3h, default=00h).................46 8.8.13 gpe1_sts_0 to smi# enable register (ge0_2smi) (index=e4h, default=00h)...............46 8.8.14 gpe1_sts_1 to smi# enable register (ge1_2smi) (index=e5h, default=00h)...............47 8.8.15 gpe1_sts_2 to smi# enable register (ge1_2smi) (index=e6h, default=00h)...............47 8.8.16 gpe1_sts_3 to smi# enable register (ge3_2smi) (index=e7h, default=00h)...............48 8.8.17 power on status register (ponsts) (index=e8h, default=--).........................................49 8.8.18 swc miscellaneous control register (swc_ctl) (index=f0h, default=00h)...................49 8.8.19 power on control register (ponctl) (index=f1h, default=00h, vpp) ...........................50 8.8.20 keyboard wake-up control register (kbd_ctl) (index=f2h, default=00h, vpp) ............51 8.8.21 gpe1_sts_0 to pson# enable register (ge0_2pon) (index=f3h, default=00h, vpp) .52 8.8.22 gpe1_sts_1 to pson# enable register (ge1_2pon) (index=f4h, default=00h, vpp) .52 8.8.23 gpe1_sts_2 to pson# enable register (ge1_2pon) (index=f5h, default=00h, vpp) .53 8.8.24 gpe1_sts_3 to pson# enable register (ge3_2pon) (index=f6h, default=00h, vpp) .54 8.8.25 led control register (led_ctl) (index=f7h, default=00h, vpp) ...................................54 8.8.26 keyboard code data 0-7 registers (keycd0-7) (index=f8h-ffh, default = -- ,vpp).......55 8.9 keyboard configuration registers (ldn=05h) ..............................................................................55 8.9.1 keyboard activate (index=30h, default=01h or 00h).........................................................55 8.9.2 kbc data base address msb register (index=60h, default=00h) ...................................55 8.9.3 kbc data base address lsb register (index=61h, default=60h) ....................................55 8.9.4 kbc command base address msb register (index=62h, default=00h)...........................55 8.9.5 kbc command base address lsb register (index=63h, default=64h)............................55 8.9.6 keyboard interrupt level select (index=70h, default=01h) ...............................................56 8.9.7 keyboard interrupt type (index=71h, default=02h) ...........................................................56 8.9.8 kbc special configuration register (index=f0h, default=00h) ............................................. 56 8.10 mouse configuration registers (ldn=06h)...................................................................................56 8.10.1 mouse activate (index=30h, default=00h) ........................................................................56 8.10.2 mouse interrupt level select (index=70h, default=0ch) ...................................................... 57 8.10.3 mouse interrupt type (index=71h, default=02h)...............................................................57 8.10.4 mouse special configuration register (index=f0h, default=00h) .....................................57 8.11 gpio configuration registers (ldn=07h) ....................................................................................57 8.11.1 programmable chip select 1 base address msb register (index=60h, default=00h) ......57 8.11.2 programmable chip select 1 base address lsb register (index=61h, default=00h) .......57 8.11.3 programmable chip select 2 base address msb register (index=62h, default=00h) ......57
www.ite.com.tw IT8780F v0.3 iv IT8780F 8.11.4 programmable chip select 2 base address lsb register (index=63h, default=00h) .......58 8.11.5 gpio(w) set 1, 2, 3, 4, 5, and 6 pin polarity registers (index=b0h, b1h, b2h, b3h, b4h, and b5h, default=00h) .....................................................................................................58 8.11.6 gpio(w) set 1, 2, 3, 4, 5, and 6 pin internal pull-up enable registers (index=b8h, b9h, bah, bbh, bch, and bdh, default=00h) ...........................................................................58 8.11.7 simple i/o set 1, 2, 3, 4, 5, and 6 data registers (index=c0h, c1h, c2h, c3h, c4h, and c5h, default=00h) ............................................................................................................58 8.11.8 simple i/o set 1, 2, 3, 4, 5, and 6 input/output selection registers (index=c8h, c9h, cah, cbh, cch, and cdh, default=00h) ...................................................................................58 8.11.9 irq3-7, 9-12 and 14-15 external routing input pin mapping registers (index=e3h-e7h, e9h-ech and eeh-efh, default=00h) ..............................................................................59 8.11.10 programmable chip select configuration registers (index=f0h, default=00h) .................59 8.11.11 user-defined memory base address high byte register (index=f1h, default=00h)..........59 8.11.12 user-defined memory base address low byte register (index=f2h, default=00h)...........59 8.11.13 user-defined memory size high byte register (index=f3h, default=00h).........................60 8.11.14 user-defined memory size low byte register (index=f4h, default=00h) .........................60 8.12 rtc configuration registers (ldn=08h) ......................................................................................61 8.12.1 rtc activate (index=30h, default=00h or 01h).................................................................61 8.12.2 rtc primary base address msb register (index=60h, default=00h) ................................61 8.12.3 rtc primary base address lsb register (index=61h, default=70h) .................................61 8.12.4 rtc secondary base address msb register (index=62h, default=00h)............................61 8.12.5 rtc secondary base address lsb register (index=63h, default=72h).............................61 8.12.6 rtc interrupt level select (index=70h, default=08h) .......................................................61 8.12.7 rtc interrupt type (index=71h, default=02h) ..................................................................62 8.12.8 rtc special configuration register (index=f0h, default=00h).........................................62 9. functional description ......................................................................................................... ...................65 9.1 lpc interface .................................................................................................................. .............65 9.1.1 lpc transactions.............................................................................................................65 9.1.2 ldrq# encoding .............................................................................................................65 9.2 serialized irq................................................................................................................. .............65 9.2.1 continuous mode .............................................................................................................65 9.2.2 quiet mode ..................................................................................................................... .66 9.2.3 waveform samples of serirq sequence .......................................................................66 9.2.4 serirq sampling slot ....................................................................................................67 9.3 general purpose i/o ............................................................................................................ ........68 9.3.1 serial bus ..................................................................................................................... ...69 9.3.2 the extended interface ....................................................................................................69 9.3.2.1 the flash rom i/f and the user-defined memory extension ...............................69 9.3.2.2 the programmable chip selects extension..........................................................70 9.4 system wake-up control (swc) and acpi ..................................................................................71 9.4.1 swc general description ................................................................................................71 9.4.2 acpi registers ................................................................................................................7 2 9.4.2.1 pm1 status block b low register (pm1b_sts_low)..........................................72 9.4.2.2 pm1 status block b high register (pm1b_sts_high) ........................................73 9.4.2.3 pm1 enable block b low register (pm1b_en_low)...........................................73 9.4.2.4 pm1 enable block b high register (pm1b_en_ high) ........................................74 9.4.2.5 pm1 control block b low register (pm1b_ cnt _low) ......................................74 9.4.2.6 pm1 control block b high register (pm1b_ cnt _high) ....................................74 9.4.2.7 general purpose 1 status 0 register (gpe1_sts_0) ..........................................75 9.4.2.8 general purpose 1 status 1 register (gpe1_sts_1) ..........................................75 9.4.2.9 general purpose 1 status 2 register (gpe1_sts_2) ..........................................75 9.4.2.10 general purpose 1 status 3 register (gpe1_sts_3) ..........................................77
www.ite.com.tw IT8780F v0.3 v contents 9.4.2.11 general purpose 1 enable 0 register (gpe1_en_0) ...........................................78 9.4.2.12 general purpose 1 enable 1 register (gpe1_en_1) ...........................................78 9.4.2.13 general purpose 1 enable 2 register (gpe1_en_2) ...........................................79 9.4.2.14 general purpose 1 enable 3 register (gpe1_en_3) ...........................................80 9.5 real time clock (rtc) .......................................................................................................... ......81 9.5.1 general description .........................................................................................................81 9.5.2 registers ...................................................................................................................... ...81 9.5.2.1 partition ...............................................................................................................81 9.5.2.2 register description.............................................................................................81 9.5.2.2.1 rtc control register a (cra), bank 0..........................................83 9.5.2.2.2 rtc control register b (crb), bank 0..........................................84 9.5.2.2.3 rtc control register c (crc), bank 0 .........................................85 9.5.2.2.4 rtc control register d (crd), bank 0 .........................................85 9.5.2.2.5 the function of wake-up alarm, bank 2........................................86 9.6 floppy disk controller (fdc)................................................................................................... .....86 9.6.1 introduction ................................................................................................................... ...86 9.6.2 reset .......................................................................................................................... .....86 9.6.3 hardware reset (lreset# pin) ......................................................................................86 9.6.4 software reset (dor reset and dsr reset) ..................................................................87 9.6.5 digital data separator ......................................................................................................87 9.6.6 write precompensation ....................................................................................................87 9.6.7 data rate selection .........................................................................................................87 9.6.8 status, data and control registers ..................................................................................87 9.6.8.1 digital output register (dor, fdc base address + 02h).....................................87 9.6.8.2 tape drive register (tdr, fdc base address + 03h) .........................................88 9.6.8.3 main status register (msr, fdc base address + 04h) .......................................88 9.6.8.4 data rate select register (dsr, fdc base address + 04h)................................89 9.6.8.5 data register (fifo, fdc base address + 05h) ..................................................90 9.6.8.6 digital input register (dir, fdc base address + 07h) .........................................90 9.6.8.7 diskette control register (dcr, fdc base address + 07h) .................................90 9.6.9 controller phases.............................................................................................................9 0 9.6.9.1 command phase .................................................................................................91 9.6.9.2 execution phase ..................................................................................................91 9.6.9.3 result phase .......................................................................................................91 9.6.9.4 result phase status registers.............................................................................91 9.6.10 command set ..................................................................................................................93 9.6.11 data transfer commands .............................................................................................. 104 9.6.11.1 read data ...................................................................................................... 104 9.6.11.2 read deleted data ..................................................................................... 105 9.6.11.3 read a track ................................................................................................ 105 9.6.11.4 write data..................................................................................................... 105 9.6.11.5 write deleted data.................................................................................... 105 9.6.11.6 format a track ........................................................................................... 105 9.6.11.7 scan ................................................................................................................ 106 9.6.11.8 verify ............................................................................................................. 106 9.6.12 control commands ........................................................................................................ 107 9.6.12.1 read id............................................................................................................ 107 9.6.12.2 configure ..................................................................................................... 108 9.6.12.3 re-calibrate................................................................................................. 108 9.6.12.4 seek................................................................................................................. 108 9.6.12.5 relative seek ............................................................................................... 109 9.6.12.6 dumpreg ........................................................................................................ 109
www.ite.com.tw IT8780F v0.3 vi IT8780F 9.6.12.7 lock................................................................................................................. 109 9.6.12.8 version .......................................................................................................... 109 9.6.12.9 sense interrupt status........................................................................... 109 9.6.12.10 sense drive status .................................................................................... 109 9.6.12.11 specify ........................................................................................................... 110 9.6.12.12 perpendicular mode ................................................................................. 111 9.6.12.13 invalid ............................................................................................................ 111 9.6.13 dma transfers............................................................................................................... 111 9.6.14 low power mode ........................................................................................................... 111 9.7 serial port (uart) description ................................................................................................. .. 112 9.7.1 data registers ............................................................................................................... 11 2 9.7.2 control registers: ier, iir, fcr, dll, dlm, lcr and mcr .......................................... 113 9.7.3 status registers: lsr and msr..................................................................................... 118 9.7.4 reset .......................................................................................................................... ... 121 9.7.5 programming ................................................................................................................. 121 9.7.6 software reset .............................................................................................................. 121 9.7.7 clock input operation..................................................................................................... 121 9.7.8 fifo interrupt mode operation ...................................................................................... 122 9.8 smart card reader .............................................................................................................. ...... 123 9.8.1 features ....................................................................................................................... . 123 9.8.2 operation ...................................................................................................................... . 123 9.8.3 connection of ifd to icc socket.................................................................................... 123 9.8.4 baud rate relationship between uart and smart card interface................................. 124 9.8.5 waveform relationship .................................................................................................. 124 9.8.6 clock divider.................................................................................................................. 124 9.8.7 waveform example of activation/deactivation sequence ............................................... 125 9.8.8 atr and pts structure.................................................................................................. 125 9.8.9 smart card operating sequence example ..................................................................... 126 9.9 parallel port .................................................................................................................. ............. 127 9.9.1 spp and epp modes ..................................................................................................... 127 9.9.2 epp mode operation ..................................................................................................... 129 9.9.3 ecp mode operation ..................................................................................................... 130 9.10 keyboard controller (kbc) ...................................................................................................... ... 137 9.10.1 host interface................................................................................................................. 138 9.10.2 data registers and status register................................................................................ 138 9.10.3 keyboard and mouse interface....................................................................................... 139 9.10.4 kirq and mirq............................................................................................................. 139 10. dc electrical characteristics.................................................................................................. ............... 141 11. ac characteristics (vcc = 5v 5%, ta = 0 c to + 70 c) ..................................................................... 143 11.1 clock input timings............................................................................................................ ........ 143 11.2 lclk (pciclk) and lreset# timings ..................................................................................... 143 11.3 lpc and serirq timings ......................................................................................................... 144 11.4 serial port, askir, sir and consumer remote control timings ................................................ 145 11.5 modem control timings .......................................................................................................... ... 145 11.6 floppy disk drive timings ...................................................................................................... .... 146 11.7 epp address or data write cycle timings ................................................................................. 147 11.8 epp address or data read cycle timings ................................................................................. 148 11.9 ecp parallel port forward timings ............................................................................................ 14 8 11.10 ecp parallel port backward timings.............................................................................. 149 12. package information............................................................................................................ ................. 151 13. ordering information........................................................................................................... .................. 153
www.ite.com.tw IT8780F v0.3 vii contents figures figure 7-1. IT8780F power control suggestion applications circuitry...........................................................2 3 figure 9-1. start frame timing ................................................................................................. ...................66 figure 9-2. stop frame timing.................................................................................................. ...................66 figure 9-3. general logic of gpiow function .................................................................................... .........68 tables table 4-1. pins listed in numeric order ........................................................................................ .................8 table 5-1. pin description of supplies signals ................................................................................. ............11 table 5-2. pin description of lpc bus interface signals........................................................................ .......11 table 5-3. pin description of sm bus interface signals ......................................................................... .......11 table 5-6. pin description of serial port 2 signals............................................................................ ............13 table 5-7. pin description of parallel port signals............................................................................ ............14 table 5-8. pin description of floppy disk controller signals................................................................... ......15 table 5-10. pin description of smart card reader interface signals ............................................................1 6 table 5-11. pin description of keyboard controller signals ..................................................................... .....17 table 5-12. pin description of real time clock signals ......................................................................... ......17 table 5-13. system wake-up and acpi signals.................................................................................... .......17 table 5-14. pin description of flash rom i/f and programmable chip select signals .................................18 table 5-15. pin description of miscellaneous signals........................................................................... ........20 table 6-1. general purpose i/o group 1 (set 1)................................................................................. ..........21 table 6-2. general purpose i/o group 2 (set 2)................................................................................. ..........21 table 6-3. general purpose i/o group 3 (set 3)................................................................................. ..........21 table 6-4. general purpose i/o group 4 (set 4)................................................................................. ..........22 table 6-5. general purpose i/o group 5 (set 5)................................................................................. ..........22 table 8-1. global configuration registers ...................................................................................... ..............26 table 8-2. fdc configuration registers ......................................................................................... ..............27 table 8-3. serial port 1 configuration registers............................................................................... ............27 table 8-4. serial port 2 configuration registers............................................................................... ............27 table 8-5. parallel port configuration registers ............................................................................... ............27 table 8-7. swc and acpi configuration registers ................................................................................ ......28 table 8-8. swc and acpi configuration registers [cont?d] ....................................................................... ...29 table 8-9. keyboard configuration registers .................................................................................... ...........29 table 8-10. mouse configuration registers...................................................................................... ............29 table 8-12. gpio configuration registers ....................................................................................... ............30 table 8-13. rtc configuration registers ........................................................................................ .............31 table 8-15. pson# and pwureq# as a function of the resume mode. ....................................................51
www.ite.com.tw IT8780F v0.3 viii IT8780F table 9-1. acpi registers...................................................................................................... ......................72 table 9-2. rtc register list, bank 0 (primary address, default = 70h/71h) .................................................82 table 9-3. rtc register list, bank 1 (second address, default = 72h/73h)..................................................82 table 9-4. rtc register list, bank 2 (second address, default = 72h/73h)..................................................82 table 9-5. digital output register (dor) ....................................................................................... ..............87 table 9-6. tape drive register (tdr) ........................................................................................... ...............88 table 9-7. main status register (msr) .......................................................................................... ..............88 table 9-8. data rate select register (dsr)..................................................................................... ............89 table 9-9. data register (fifo)................................................................................................ ...................90 table 9-10. digital input register (dir) ....................................................................................... .................90 table 9-11. diskette control register (dcr) .................................................................................... ............90 table 9-12. status register 0 (st0) ............................................................................................ .................91 table 9-13. status register 1 (st1) ............................................................................................ .................92 table 9-14. status register 2 (st2) ............................................................................................ .................92 table 9-15. status register 3 (st3) ............................................................................................ .................93 table 9-16. command set symbol descriptions.................................................................................... .......94 table 9-17. command set summary ................................................................................................ ...........96 table 9-18. effects of mt and n bits ........................................................................................... ............... 104 table 9-19. scan command result ................................................................................................ .......... 106 table 9-20. verify command result .............................................................................................. ......... 107 table 9-21. interrupt identification ........................................................................................... ................... 109 table 9-22. hut values......................................................................................................... .................... 110 table 9-23. srt values......................................................................................................... .................... 110 table 9-24. hlt values ......................................................................................................... .................... 110 table 9-25. effects of gap and wg on format a track and write data commands....................... 111 table 9-26. effects of drive mode and data rate on format a track and write data commands... 111 table 9-27. serial channel registers ........................................................................................... .............. 112 table 9-28. interrupt enable register description .............................................................................. ........ 113 table 9-29. interrupt identification register .................................................................................. .............. 114 table 9-30. fifo control register description .................................................................................. ......... 115 table 9-31. receiver fifo trigger level encoding ............................................................................... .....115 table 9-32. baud rates using (24 mhz 13) clock................................................................................... 116 table 9-33. line control register description .................................................................................. .......... 117 table 9-34. stop bits number encoding.......................................................................................... ........... 117 table 9-35. modem control register description ................................................................................. ...... 118 table 9-36. line status register description................................................................................... ........... 118 table 9-37. modem status register description.................................................................................. ....... 120 table 9-38. reset control of registers and pinout signals...................................................................... ... 121 table 9-39. scrclk selections .................................................................................................. .............. 124
www.ite.com.tw IT8780F v0.3 ix contents table 9-40. parallel port connector in different modes ......................................................................... .....127 table 9-41. address map and bit map for spp and epp modes ................................................................ 127 table 9-42. bit map of the ecp registers ....................................................................................... ........... 130 table 9-43. ecp register definitions ........................................................................................... .............. 131 table 9-44. ecp mode descriptions.............................................................................................. ............. 131 table 9-45. ecp pin descriptions ............................................................................................... ............... 132 table 9-46. extended control register (ecr) mode and description ......................................................... 134 table 9-47. data register read/write controls .................................................................................. ... 138 table 9-48. status register.................................................................................................... .................... 138

www.ite.com.tw IT8780F v0.3 itpm-pn-200305 specifications subject to change without notice joseph haung, 02/12/2003 1 features 1. features low pin count interface ? ? ? ? compliant with intel low pin count interface specification rev. 1.0 (sept. 29, 1997) ? ? ? ? supports ldrq#, serirq protocols two 16c550 uarts ? ? ? ? supports two standard serial ports ? ? ? ? maximum data rate up to 1.5 mbps ? ? ? ? supports smart card reader protocols smart card reader ? ? ? ? compliant with personal computer smart card (pc/sc) working group standard ? ? ? ? compliant with smart card (iso 7816) protocols ? ? ? ? supports card present detect ? ? ? ? supports one programmable clock frequency, 7.1 mhz, and 3.5 mhz (default) card clocks ieee 1284 parallel port ? ? ? ? standard mode -- bi-directional spp compliant ? ? ? ? enhanced mode -- epp v. 1.7 and v. 1.9 compliant ? ? ? ? high speed mode -- ecp, ieee 1284 compliant ? ? ? ? back-drive current reduction ? ? ? ? printer power-on damage reduction ? ? ? ? supports post (power-on self test) data port floppy disk controller ? ? ? ? supports two 360k/720k/1.2m/1.44m/2.88m floppy disk drives ? ? ? ? enhanced digital data separator ? ? ? ? 3-mode drives supported ? ? ? ? supports write protection via software keyboard controller ? ? ? ? 8042 compatible for ps/2 keyboard and mouse ? ? ? ? 2kb of programmable rom and 256-byte data ram ? ? ? ? gatea20 and keyboard reset output ? ? ? ? supports keyboard and mouse i/f hardware auto-swap extended i/f ? ? ? ? provides flash rom i/f and user-defined memory extension ? ? ? ? provides 2 programmable chip selects for the i/o devices. 43 general purpose i/o pins ? ? ? ? gpio pins can be individually enabled or disabled via software configuration registers ? ? ? ? gpio pins can be individually set as input or output via software configuration registers ? ? ? ? supports 16 programmable de-bouncing inputs and two blinking outputs ? ? ? ? some gpio pins are powered by vsb and can be used as power-up events external irq input routing capability ? ? ? ? provides irq input routing through gpio input mode real time clock (rtc) ? ? ? ? 146818 compatible with 242-byte cmos ram ? ? ? ? binary or bcd data format for time, alarm and calendar ? ? ? ? time of century wake-up alarm ? ? ? ? 12/24 hour format for hour register and alarm hour register acpi ? ? ? ? acpi 1.0b compliant ? ? ? ? power up events: irq, kbd, mouse, ring indicator, gpio, power button, ? ? ? ? ? generation of siosmi# ? ? ? ? individual function enable/disable control bits sm bus slave ? ? ? ? accessing internal registers clocks ? ? ? ? 33 mhz lpc clock input ? ? ? ? 48 mhz system clock input ? ? ? ? 32.768 khz oscillator circuit for rtc ? ? ? ? 40 mhz and 1 hz outputs power supply ? ? ? ? +3.3v pad with 5v tolerance; +3.3v core ? ? ? ? v_battery (vbat) for rtc ? ? ? ? v_standby (vsb) supported package: 128-pin qfp
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www.ite.com.tw IT8780F v0.3 3 general description 2. general description the IT8780F is a low pin count interface-based highly integrated super i/o. the IT8780F provides the most commonly used legacy super i/o functionality plus the real time clock (rtc) and smart card reader interface. the device?s lpc interface complies with intel ?lpc interface specification rev. 1.0?. the IT8780F meets the ?microsoft ? pc98 & pc99 system design guide? requirements. the IT8780F has integrated 8 logical devices. one high-performance 2.88mb floppy disk controller, with digital data separator, supports two 360k/720k/1.2m/1.44m/2.88m floppy disk drives. one multi-mode high- performance parallel port features the bi-directional standard parallel port (spp), the enhanced parallel port (epp v. 1.7 and epp v. 1.9 are supported), and the ieee 1284 compliant extended capabilities port (ecp). two 16c550 standard compatible enhanced uarts perform asynchronous communication. the IT8780F also has an integrated 8042 compatible keyboard controller with 2kb of programmable rom for customer application and a 146818-compatible real time clock with 242-byte cmos ram. IT8780F provides an extended i/f to lpc bus to enable the isa-like external 8-bit peripherals, including the flash rom i/f. it also provides 43 general purpose i/o pins (multi-function pins) and sm bus slave mode to access the chip configuration registers. these 8 logical devices can be individually enabled or disabled via software configuration registers. the IT8780F utilizes power-saving circuitry to reduce power consumption, and once a logical device is disabled, the inputs are gated inhibit, the outputs are tri-state, and the input clock is disabled. the device requires a single 24/48 mhz clock input and operates with +3.3v power supply but +5v tolerance. the IT8780F is available in 128-pin qfp (quad flat package).
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www.ite.com.tw IT8780F v0.3 5 block diagram 3. block diagram pnp reg. serial irq clock gen central bus 8042 kbc 16c550 uarts smart card i/f lpc interface fdc IT8780F parallel port rtc sm bus i/f extended i/f acpi gpio port
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www.ite.com.tw IT8780F v0.3 7 pin configuration 4. pin configuration gpiow14/xa7 gpiow15/xa6 gpiow16/xa5 gpiow17/xa4 gpio55/scrst gpio56/scpwr gnd vsb gpio20/xrd#_xen gpio21/xwr#_xdir gpio22/xa3 gpio23/xa2 gpio24/xa1 gpiow40/cs2# gpio25/xa0 gpio57/hfckout gpiow41/cs1# gpio26/udmcs# gpio27/frcs# gpio30/xd7 gpio31/xd6 gpio32/xd5 gpio33/xd4 gpio36/xd1 gpio37/xd0 gpio60/xstrb2/jp4 gpio61/xstrb1/jp5 gpio52/xstrb0/jp6 pwbtin# gpiow42/slbtin# gpio35/xd2 siosmi# pson# vsb vbat x32ki gnd x32ko gpio53/lfckout sdat sclk gpio62/scio gpiow43/pwbtout# led1/gpiow44 led2/gpiow45 gpiow46/scpsnt# slp_sx#/gpiow47 gpio54/vccfail gpio51/scclk ck48mi dskchg# hdsel# rdata# wp# trk0# wgate# wdata# gpiow10/xa11 gpiow12/xa9 gpiow13/xa8 dcd2# ri1# dtr1#/jp3 cts1# sout1/jp2 dcd1# rts1#/jp1 gnd vcc stb# afd# pd0 err# pd1 init# pd2 index# slin# pd3 pd4 mtr0# pd5 pd6 pd7 ack# busy pe drv1#/kp16 slct densel drate0 gnd drv0# mtr1#/kp17 dir# vcc dsr2# sin2 rts2# sout2 cts2# dtr2# ri2# lad3 lad2 lad1 lad0 lclk gnd vcc lframe# ldrq# serirq lreset# ppdis/kp12 kbrst# ga20 gpio50/clkrun# kclk kdat mclk mdat step# sin1 dsr1# pwureq# 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 31 32 33 34 35 36 37 38 59 60 61 62 63 64 104 105 106 107 108 103 72 71 70 69 68 67 66 65 IT8780F 128-qfp gpiow11/xa10 gpio34/xd3 top view
www.ite.com.tw IT8780F v0.3 8 IT8780F table 4-1. pins listed in numeric order pin signal pin signal pin signal pin signal 1 gpiow10/xa11 33 gpio61/xstrb1/ jp5 65 dir# 97 rts1#/jp1 2 gpiow11/xa10 34 gpio52/xstrb0/ jp6 66 mtr1#/kp17 98 sout1/jp2 3 gpiow12/xa9 35 gpiow42/slbti n# 67 drv0# 99 cts1# 4 gpiow13/xa8 36 pwbtin# 68 gnd 100 dtr1#/jp3 5 gpiow14/xa7 37 siosmi# 69 vcc 101 ri1# 6 gpiow15/xa6 38 pwureq# 70 drv1#/kp16 102 dcd2# 7 gpiow16/xa5 39 pson# 71 mtr0# 103 dsr2# 8 gpiow17/xa4 40 vsb 72 index# 104 sin2 9 gpio55/scrst 41 vbat 73 drate0 105 rts2# 10 gpio56/scpwr 42 x32ki 74 densel 106 sout2 11 gnd 43 gnd 75 slct 107 cts2# 12 vsb 44 x32ko 76 pe 108 dtr2# 13 gpio57/hfckou t 45 gpio53/lfckou t 77 busy 109 ri2# 14 gpio20/xrd#_x en 46 sdat 78 ack# 110 lad3 15 gpio21/ xwr#_xdir 47 sclk 79 pd7 111 lad2 16 gpio22/xa3 48 gpio62/scio 80 pd6 112 lad1 17 gpio23/xa2 49 gpiow43/ pwbtout# 81 pd5 113 lad0 18 gpio24/xa1 50 led1/gpiow44 82 pd4 114 lclk 19 gpio25/xa0 51 led2/gpiow45 83 pd3 115 gnd 20 gpiow40/cs2# 52 gpiow46/scps nt# 84 slin# 116 vcc 21 gpiow41/cs1# 53 slp_sx#/gpiow 47 85 pd2 117 lframe# 22 gpio26/udmcs# 54 gpio54/vccfail 86 init# 118 ldrq# 23 gpio27/frcs# 55 gpio51/scclk 87 pd1 119 serirq 24 gpio30/xd7 56 ck48mi 88 err# 120 lreset# 25 gpio31/xd6 57 dskchg# 89 pd0 121 ppdis/kp12 26 gpio32/xd5 58 hdsel# 90 afd# 122 kbrst# 27 gpio33/xd4 59 rdata# 91 stb# 123 ga20 28 gpio34/xd3 60 wp# 92 vcc 124 gpio50/clkrun # 29 gpio35/xd2 61 trk0# 93 gnd 125 kclk 30 gpio36/xd1 62 wgate# 94 dcd1# 126 kdat 31 gpio37/xd0 63 wdata# 95 dsr1# 127 mclk 32 gpio60/xstrb2/ jp4 64 step# 96 sin1 128 mdat
www.ite.com.tw IT8780F v0.3 9 pin configuration table 4-2. pins listed in alphabetical order pin signal pin signal pin signal pin signal 78 ack# 23 gpio27/frcs# 52 gpiow46/scps nt# 36 pwbtin# 90 afd# 24 gpio30/xd7 58 hdsel# 38 pwureq# 77 busy 25 gpio31/xd6 72 index# 59 rdata# 56 ck48mi 26 gpio32/xd5 86 init# 101 ri1# 99 cts1# 27 gpio33/xd4 122 kbrst# 109 ri2# 107 cts2# 28 gpio34/xd3 125 kclk 97 rts1#/jp1 94 dcd1# 29 gpio35/xd2 126 kdat 105 rts2# 102 dcd2# 30 gpio36/xd1 113 lad0 47 sclk 74 densel 31 gpio37/xd0 112 lad1 46 sdat 65 dir# 124 gpio50/clkrun # 111 lad2 119 serirq 73 drate0 55 gpio51/scclk 110 lad3 96 sin1 67 drv0# 34 gpio52/xstrb0/ jp6 114 lclk 104 sin2 70 drv1#/kp16 45 gpio53/lfckou t 118 ldrq# 37 siosmi# 57 dskchg# 54 gpio54/vccfail 50 led1/gpiow44 75 slct 95 dsr1# 9 gpio55/scrst 51 led2/gpiow45 84 slin# 103 dsr2# 10 gpio56/scpwr 117 lframe# 53 slp_sx#/gpiow 47 100 dtr1#/jp3 13 gpio57/hfckou t 120 lreset# 98 sout1/jp2 108 dtr2# 32 gpio60/xstrb2/ jp4 127 mclk 106 sout2 88 err# 33 gpio61/xstrb1/ jp5 128 mdat 91 stb# 123 ga20 48 gpio62/scio 71 mtr0# 64 step# 11 gnd 1 gpiow10/xa11 66 mtr1#/kp17 61 trk0# 43 gnd 2 gpiow11/xa10 89 pd0 41 vbat 68 gnd 3 gpiow12/xa9 87 pd1 69 vcc 93 gnd 4 gpiow13/xa8 85 pd2 92 vcc 115 gnd 5 gpiow14/xa7 83 pd3 116 vcc 14 gpio20/xrd#_x en 6 gpiow15/xa6 82 pd4 12 vsb 15 gpio21/ xwr#_xdir 7 gpiow16/xa5 81 pd5 40 vsb 16 gpio22/xa3 8 gpiow17/xa4 80 pd6 63 wdata# 17 gpio23/xa2 20 gpiow40/cs2# 79 pd7 62 wgate# 18 gpio24/xa1 21 gpiow41/cs1# 76 pe 60 wp# 19 gpio25/xa0 35 gpiow42/slbti n# 121 ppdis/kp12 42 x32ki 22 gpio26/udmcs# 49 gpiow43/ pwbtout# 39 pson# 44 x32ko
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www.ite.com.tw IT8780F v0.3 11 pin descriptions 5. IT8780F pin descriptions table 5-1. pin description of supplies signals pin(s) no. symbol attribute power description 69, 92, 116 vcc pwr - +3.3v power supply. 12, 40 vsb pwr - +3.3v standby power supply. 41 vbat pwr - +3.3v battery supply. 11, 43, 68, 93, 115 gnd gnd - ground. table 5-2. pin description of lpc bus interface signals pin(s) no. symbol attribute power description 120 lreset# di vcc lpc reset #. 118 ldrq# do16 vcc lpc dma request #. an encoded signal for dma channel select. 119 serirq dio16 vcc serial irq. 117 lframe# di vcc lpc frame #. this signal indicates the start of lpc cycle. 110 ? 113 lad[3:0] dio8 vcc lpc address/data 3 - 0. 4-bit lpc address/bi-directional data lines. lad0 is the lsb and lad3 is the msb. 114 lclk di vcc lpc clock. 33 mhz lpc clock input. 124 clkrun#/ gpio50 diod8/ diod8 vsb clock run # / general purpose i/o 50. ? the first function of this pin is the clock run #. this is an open-drain output and input. the IT8780F uses this signal to request starting (or speed up) the clock. clkrun# also indicates the clock status. ? the second function of this pin is the general purpose i/o 50. ? the function configuration of this pin is decided by the software configuration registers. table 5-3. pin description of sm bus interface signals pin(s) no. symbol attribute power description 46 sdat diod8 vsb serial bus bi-directional data. the function of this pin is sm bus bi-directional data. 47 sclk di vsb serial bus clock. the function of this pin is sm bus clock.
www.ite.com.tw IT8780F v0.3 12 IT8780F table 5-4. pin description of serial port 1 signals pin(s) no. symbol attribute power description 96 sin1 di vcc serial data in 1. this input receives serial data from the communications link. 98 sout1/jp2 do8/ di vcc serial data out 1. this output sends serial data to the communications link. this signal is set to a marking state (logic 1) after a master reset operation or when the device is in one of the infrared communications modes. during lreset#, this pin is input for jp2 power-on strapping option. 95 dsr1# di vcc data set ready 1 #. when the signal is low, it indicates that the modem or data set is ready to establish a communications link. the dsr1# signal is a modem status input whose condition can be tested by reading the msr register. 97 rts1#/jp1 do8/di vcc request to send 1 #. when this signal is low, this output indicates to the modem or data set that the device is ready to send data. rts1# is activated by setting the appropriate bit in the mcr register to 1. after a master reset operation or during loop mode, rts1# is set to its inactive state. during lreset#, this pin is input for jp1 power-on strapping option. 100 dtr1#/jp3 do8/di vcc data terminal ready 1 #. dtr1# is used to indicate to the modem or data set that the device is ready to exchange data. dtr1# is activated by setting the appropriate bit in the mcr register to 1. after a master reset operation or during loop mode, dtr1# is set to its inactive state. during lreset#, this pin is input for jp3 power-on strapping option. 99 cts1# di vcc clear to send 1 #. when this signal is low, it indicates that the modem or data set is ready to accept data. the cts1# signal is a modem status input whose condition can be tested by reading the msr register. 101 ri1# di vcc ring indicator 1 #. when this signal is low, it indicates that a telephone ring signal has been received by the modem. the ri1# signal is a modem status input whose condition can be tested by reading the msr register. 94 dcd1# di vcc data carrier detect 1 #. when this signal is low, it indicates that the modem or data set has detected a carrier. the dcd1# signal is a modem status input whose condition can be tested by reading the msr register.
www.ite.com.tw IT8780F v0.3 13 pin description table 5-6. pin description of serial port 2 signals pin(s) no. symbol attribute power description 104 sin2 di vcc serial data in 2. this input receives serial data from the communications link. 106 sout2 do8 vcc serial data out 2. this output sends serial data to the communications link. this signal is set to a marking state (logic 1) after a master reset operation or when the device is in one of the infrared communications modes. 103 dsr2# di vcc data set ready 2 #. when low, indicates that the modem or data set is r eady to establish a communications link. the dsr2# signal is a modem status input whose condition can be tested by reading the msr register. 105 rts2# do8 vcc request to send 2 #. when low, this output indicates to the modem or data set that the device is ready to send data. rts2# is activated by setting the appropriate bit in the mcr register to 1. after a master reset operation or during loop mode, rts2# is set to its inactive state. 108 dtr2# do8 vcc data terminal ready 2 #. dtr2# is used to indicate to the modem or data set that the device is ready to exchange data. dtr2# is activated by setting the appropriate bit in the mcr register to 1. after a master reset operation or during loop mode, dtr2# is set to its inactive state. 107 cts2# di vcc clear to send 2 #. when low, indicates that the modem or data set is r eady to accept data. the cts2# signal is a modem status input whose condition can be tested by reading the msr register. 109 ri2# di vcc ring indicator 2 #. when low, indicates that a tele phone ring signal has b een received by the modem. the ri2# signal is a modem status input whose condition can be tested by reading the msr register. 102 dcd2# di vcc data carrier detect 2 #. when low, indicates that the modem or data set has detected a carrier. the dcd2# signal is a modem status input whose condition can be tested by reading the msr register.
www.ite.com.tw IT8780F v0.3 14 IT8780F table 5-7. pin description of parallel port signals pin(s) no. symbol attribute power description 75 slct di vcc printer select. this signal goes high when the line printer has been selected. 76 pe di vcc printer paper end. this signal is set high by the printer when it runs out of paper. 77 busy di vcc printer busy. this signal goes high when the line printer has a local operation in progress and cannot accept data. 78 ack# di vcc printer acknowledge #. this signal goes low to indicate that the printer has already received a character and is ready to accept another. 84 slin# do 16/24 vcc printer select input #. when low, the printer is selected. this signal is derived from the complement of bit 3 of the printer control register. 86 init# do 16/24 vcc printer initialize #. active low. this signal is derived from bit 2 of the printer control register, and is used to initialize the printer. 88 err# di vcc printer error #. when low, it indicates that the printer has encountered an error. the error message can be read from bit 3 of the printer status register. 90 afd# do 16/24 vcc printer auto line feed #. active low. this signal is derived from the complement of bit 1 of the printer control register, and is used to advance one line after each line is printed. 91 stb# do 16/24 vcc printer strobe #. active low. this signal is the complement of bit 0 of the printer control register, and is used to strobe the printing data into the printer. 79?83, 85, 87, 89 pd[7:0] dio 16/24 vcc parallel port data bus. this bus provides a byte-wide input or output to the system. the eight lines are held in a high impedance state when the port is deselected. 121 ppdis/ kp12 di/ diod8 vcc parallel port disable/ kbc i/o port 12. ? the first function of this pin is parallel port disable. when high, this input disables all the output signals of the parallel port. ? the second function of this pin is the kbc i/o port 12. ? the function configuration of this pin is decided by the software configuration registers.
www.ite.com.tw IT8780F v0.3 15 pin description table 5-8. pin description of floppy disk controller signals pin(s) no. symbol attribute power description 74 densel do 4/24 vcc fdd density select. densel is high for high data rates (500 kbps, 1 mbps). densel is low for low data rates (250 kbps, 300 kbps). 73 drate0 do 4/24 vcc data rate 0. drate0 reflects the currently selected fdc data rate, or the data rate select register (dsr). 71 mtr0# do 4/24 vcc fdd motor 0 enable #. active low. mtr0# is controlled by the digital output register (dor). 66 mtr1#/ kp17 do 4/24 / diod 4/24 vcc fdd motor 1 enable #/ kbc i/o port 17. ? the first function of this pin is the motor enable line for fdd drive 1. this is an active low signal, and is controlled by the digital output register (dor). ? the second function of this pin is the kbc i/o port 17. ? the function configuration of this pin is decided by the software configuration registers. 70 drv1#/ kp16 do 4/24 / diod 4/24 vcc fdd drive 1 enable #/ kbc i/o port 16. ? the first function of this pin is the decoded drive select output for fdd drive 1. this is an active low signal, and is controlled by the digital output register (dor). ? the second function of this pin is the kbc i/o port 16. ? the function configuration of this pin is decided by the software configuration registers. 67 drv0# do 4/24 vcc fdd drive 0 enable #. active low. drv0# is controlled by the digital output register (dor). 63 wdata# do 4/24 vcc fdd write serial data to the drive #. active low. 65 dir# do 4/24 vcc fdd head direction #. step in when low and step out when high during a seek operation. 64 step# do 4/24 vcc fdd step pulse #. active low. 58 hdsel# do 4/24 vcc fdd head select #. active low. 62 wgate# do 4/24 vcc fdd write gate enable # active low. 59 rdata# di vcc fdd read disk data #. active low, serial data input from fdd. 61 trk0# di vcc fdd track 0 #. active low. indicates that the head of the selected drive is on track 0. 72 index# di vcc fdd index #. active low. indicates the beginning of a disk track. 60 wp# di vcc fdd write protect #. active low. indicates that the disk of the selected drive is write-protected. 57 dskchg# di vcc floppy disk change #. active low. this input pin senses whether the drive door has been opened or a diskette has been changed.
www.ite.com.tw IT8780F v0.3 16 IT8780F table 5-10. pin description of smart card reader interface signals pin(s) no. symbol attribute power description 9 gpio55/ scrst diod8/ dod8 vsb general purpose i/o 55 / smart card reset. ? the first function of this pin is the general purpose i/o 55. ? the second function of this pin is smart card reset. ? the function configuration of this pin is decided by the software configuration registers. 10 gpio56/ scpwr diod8/ dod8 vsb general purpose i/o 56 / smart card power fet control output. ? the first function of this pin is the general purpose i/o 56. ? the second function of this pin is smart card power fet control output #. the smart card reader interface requires this pin to drive an external power fet to supply the current for the smart card (65 ma typical, 100 ma short to ground). ? the function configuration of this pin is decided by the software configuration registers. 48 gpio62/ scio diod8/ diod8 vsb general purpose i/o 62 / smart card serial data i/o. ? the first function of this pin is the general purpose i/o 62. ? the second function of this pin is smart card serial data i/o. ? the function configuration of this pin is decided by the software configuration registers. 52 gpiow46/ scpsnt# diod8/ di vsb general purpose i/o/wake-up event 46 / smart card present detect #. ? the first function of this pin is the general purpose i/o and wake-up event input 46. ? the second function of this pin is smart card present detect #. this pin provides the smart card insertion detection for the smart card reader interface. upon detecting the insertion of the smart card, this pin will trigger the power-on event. ? the function configuration of this pin is decided by the software configuration registers. 55 gpio51/ scclk diod8/ dod8 vsb general purpose i/o 51 / smart card clock. ? the first function of this pin is the general purpose i/o 51. ? the second function of this pin is smart card clock. three different card clocks are selectable from this pin: high speed (7.1 mhz), low speed (default: 3.5 mhz) and a programmable card clock. ? the function configuration of this pin is decided by the software configuration registers.
www.ite.com.tw IT8780F v0.3 17 pin description table 5-11. pin description of keyboard controller signals pin(s) no. symbol attribute power description 126 kdat diod16 vsb keyboard data. 125 kclk diod16 vsb keyboard clock. 128 mdat diod16 vsb ps/2 mouse data. 127 mclk diod16 vsb ps/2 mouse clock. 122 krst# do8 vcc keyboard reset #. 123 ga20 do8 vcc gate address 20. table 5-12. pin description of real time clock signals pin(s) no. symbol attribute power description 42 x32ki osci vpp crystal input. input signal to the rtc crystal oscillator. 44 x32ko osco vpp crystal output. output signal from the rtc crystal oscillator. table 5-13. system wake-up and acpi signals pin(s) no. symbol attribute power description 36 pwbtin# di vsb main power switch button input #. active low. 35 slbtin#/ gpiow42 di/ diod8 vsb sleep button input #/ general purpose i/o/wake-up event 42. ? the first function of this pin is sleep button input #. ? the second function of this pin is the general purpose i/o and wake-up event input 42. ? the function configuration of this pin is decided by the software configuration registers. 37 siosmi# dod8 vsb system management interrupt #. active low. 38 pwureq# dod8 vsb power-up request output #. active (low) level indicates that a wake-up event has occurred, and the system should exit its current sleep state. 39 pson# dod8 vsb power supply on/off control #. active (low) level indicates that the power should be turned on. 50?51 led[1:2]/ gpiow 4[4:5] dod8/ diod8 vsb led control [1:2]/ general purpose i/o/wake-up event 4[4:5]. ? the first functions of these pins are led control [1:2]. ? the second functions of these pins are the general purpose i/o and wake-up event input 4[4:5]. ? the function configuration of this pin is decided by the software configuration registers. 53 slp_sx#/ gpiow47 di/ diod8 vsb chipset sleep state input #/ general purpose i/o/wake- up event 47. ? the first function of this pin is chipset sleep state input #. ? the second function of this pin is the general purpose i/o and wake-up event input 47. ? the function configuration of this pin is decided by the software configuration registers. 54 vccfail/ gpio54 do8/ diod8 vsb vcc failing / general purpose i/o 54. ? the first function of this pin is vcc failing. ? the second function of this pin is the general purpose i/o 54. ? the function configuration of this pin is decided by the software configuration registers.
www.ite.com.tw IT8780F v0.3 18 IT8780F table 5-14. pin description of flash rom i/f and programmable chip select signals pin(s) no. symbol attribute power description 1?8 gpiow1[0:7]/ xa[11:4] diod8/ do8 vsb general purpose i/o/wake-up event 1[0:7] / x addresses [11:4]. ? the first functions of these pins are the general purpose i/o and wake-up event input 1[0:7]. ? the second functions of these pins are x addresses [11:4]. ? the function configuration of this pin is decided by the software configuration registers. 14 gpio20/ xrd#_xen diod8/ do8 vsb general purpose i/o 20 / x read #/data enable. ? the first function of this pin is the general purpose i/o 20. ? the second function of this pin is x read strobe # or x-data enable. an active low level of xrd# indicates a read cycle. an active high level of xen indicates valid data on the xd bus. ? the function configuration of this pin is decided by the software configuration registers. 15 gpio21/ xwr#_xdir diod8/ do8 vsb general purpose i/o 21 / x write #/data direction. ? the first function of this pin is general purpose i/o 21. ? the second function of this pin is x write strobe # or x-data direction. an active low level of xwr# indicates a write cycle. a high level of xdir indicates a read cycle on the xd bus; a low level of xdir indicates a write cycle on the xd bus. ? the function configuration of this pin is decided by the software configuration registers. 16?19 gpio2[2:5]/ xa[3:0] diod8/ do8 vsb general purpose i/o 2[2:5] / x addresses [3:0]. ? the first functions of these pins are general purpose i/o 2[2:5]. ? the second functions of these pins are x addresses [3:0]. ? the function configuration of this pin is decided by the software configuration registers. 20?21 gpiow4[0:1]/ cs[2:1]# diod8/ do8 vsb general purpose i/o/wake-up event 4[0:1] / programmable chip select [2:1] #. ? the first functions of these pins are general purpose i/o and wake-up event input 4[0:1]. ? the second functions of these pins are programmable chip select [2:1]#. ? the function configuration of this pin is decided by the software configuration registers. 22 gpio26/ udmcs# diod8/ do8 vsb general purpose i/o 26 / user-defined memory chip select #. ? the first function of this pin is general purpose i/o 26. ? the second function of this pin is user-defined memory chip select #. ? the function configuration of this pin is decided by the software configuration registers.
www.ite.com.tw IT8780F v0.3 19 pin description pin description of flash rom i/f and programmable chip select signals [cont?d] pin(s) no. symbol attribute power description 23 gpio27/ frcs# diod8/ do8 vsb general purpose i/o 27 / flash rom i/f chip select #. ? the first function of this pin is the general purpose i/o 27. ? the second function of this pin is flash rom i/f chip select #. ? the function configuration of this pin is decided by the software configuration registers. 24?31 gpio3[0:7]/ xd[7:0] diod8/ diod8 vsb general purpose i/o 3[0:7] / x data [7:0]. ? the first functions of these pins are general purpose i/o 3[0:7]. ? the second functions of these pins are x data [7:0]. ? the function configuration of this pin is decided by the software configuration registers. 32?33 gpio6[0:1]/ xstrb[2:1]/ jp[4:5] diod8/ do8/ di vsb general purpose i/o 6[0:1] / x address strobes [2:1] / jp [4:5]. ? the first functions of these pins are general purpose i/o 6[0:1]. ? the second functions of these pins are x data [2:1]. ? the function configuration of this pin is decided by the software configuration registers. during vsb power-on and lreset# activation, these pins are inputs for jp[4:5] power-on strapping option. a weak internal pull-down will be active during the same moment. 34 gpio52/ xstrb0/ jp6 diod8/ do8/ di vsb general purpose i/o 52 / x address strobe 0 / jp6. ? the first function of this pin is the general purpose i/o 52. ? the second function of this pin is x address strobe 0. ? the function configuration of this pin is decided by the software configuration registers. during vsb power-on and lreset# activation, these pins are inputs for jp6 power-on strapping option. a weak internal pull-down will be active during the same moment.
www.ite.com.tw IT8780F v0.3 20 IT8780F table 5-15. pin description of miscellaneous signals pin(s) no. symbol attribute power description 13 gpio57/ hfckout diod8/ do8 vsb general purpose i/o 57 / high frequency clock output. ? the first function of this pin is the general purpose i/o 57. ? the second function of this pin is high frequency clock output. ? the function configuration of this pin is decided by the software configuration registers. 45 gpio53/ lfckout diod8/ do8 vsb general purpose i/o 53 / low frequency clock output. ? the first function of this pin is the general purpose i/o 53. ? the second function of this pin is low frequency clock output. ? the function configuration of this pin is decided by the software configuration registers. 49 gpiow43/ pwbtout# diod8/ dod8 vsb general purpose i/o/wake-up event 43 / power button output. ? the first function of this pin is the general purpose i/o and wake-up event input 43. ? the second function of this pin is power button output. ? the function configuration of this pin is decided by the software configuration registers. 56 ck48mi di vsb clock input. 48 mhz clock input. io cell: do8: sourcing/sinking 8ma digital output buffer dod8: sinking 8ma digital open-drain output buffer do16: souring/sinking 16ma digital output buffer do 4/24 : sourcing 4ma/sinking 24ma digital output buffer do 16/24 : sourcing 16ma/sinking 24ma digital output buffer dio8: sourcing/sinking 8ma digital input/output buffer diod8: sinking 8ma digital open-drain input/output buffer dio16: sourcing/sinking 16ma digital input/output buffer diod16: sinking16ma digital open-drain input/output buffer dio 4/24 : sourcing 4ma/sinking 24ma digital input/output buffer dio 16/24 : sourcing 16ma/sinking 24ma digital input/output buffer osco: crystal oscillator output buffer di: digital input osci: crystal oscillator input buffer
www.ite.com.tw IT8780F v0.3 21 list of gpio pins 6. list of gpio pins table 6-1. general purpose i/o group 1 (set 1) signal pin # attribute description gpiow10/xa11 1 diod8/do8 general purpose i/o/wake-up event 10 / x address 11. gpiow11/xa10 2 diod8/do8 general purpose i/o/wake-up event 11 / x address 10. gpiow12/xa9 3 diod8/do8 general purpose i/o/wake-up event 12 / x address 9. gpiow13/xa8 4 diod8/do8 general purpose i/o/wake-up event 13 / x address 8. gpiow14/xa7 5 diod8/do8 general purpose i/o/wake-up event 14 / x address 7. gpiow15/xa6 6 diod8/do8 general purpose i/o/wake-up event 15 / x address 6. gpiow16/xa5 7 diod8/do8 general purpose i/o/wake-up event 16 / x address 5. gpiow17/xa4 8 diod8/do8 general purpose i/o/wake-up event 17 / x address 4. table 6-2. general purpose i/o group 2 (set 2) signal pin # attribute description gpio20/xrd#_xen 14 diod8/do8 general purpose i/o 20 / x read #/data enable. gpio21/xwr#_xdir 15 diod8/do8 general purpose i/o 21 / x write #/data direction. gpio22/xa3 16 diod8/do8 general purpose i/o 22 / x address 3. gpio23/xa2 17 diod8/do8 general purpose i/o 23 / x address 2. gpio24/xa1 18 diod8/do8 general purpose i/o 24 / x address 1. gpio25/xa0 19 diod8/do8 general purpose i/o 25 / x address 0. gpio26/udmcs# 22 diod8/do8 general purpose i/o 26 / user-defined memory chip select #. gpio27/frcs# 23 diod8/do8 general purpose i/o 27 / flash rom i/f chip select #. table 6-3. general purpose i/o group 3 (set 3) signal pin # attribute description gpio30/xd7 24 diod8/diod8 general purpose i/o 30 / x data 7. gpio31/xd6 25 diod8/diod8 general purpose i/o 31 / x data 6. gpio32/xd5 26 diod8/diod8 general purpose i/o 32 / x data 5. gpio33/xd4 27 diod8/diod8 general purpose i/o 33 / x data 4. gpio34/xd3 28 diod8/diod8 general purpose i/o 34 / x data 3. gpio35/xd2 29 diod8/diod8 general purpose i/o 35 / x data 2. gpio36/xd1 30 diod8/diod8 general purpose i/o 36 / x data 1. gpio37/xd0 31 diod8/diod8 general purpose i/o 37 / x data 0.
www.ite.com.tw IT8780F v0.3 22 IT8780F table 6-4. general purpose i/o group 4 (set 4) signal pin # attribute description gpiow40/cs2# 20 diod8/do8 general purpose i/o/wake-up event 40 / programmable chip select 2 #. gpiow41/cs1# 21 diod8/do8 general purpose i/o/wake-up event 41 / programmable chip select 1 #. gpiow42/slbtin# 35 diod8/di general purpose i/o/wake-up event 42 / sleep button input #. gpiow43/ pwbtout# 49 diod8/dod8 general purpose i/o/wake-up event 43 / power button output #. gpiow44/led1 50 diod8/dod8 general purpose i/o/wake-up event 44 / led control 1. gpiow45/led2 51 diod8/dod8 general purpose i/o/wake-up event 45 / led control 2. gpiow46/ scpsnt# 52 diod8/di general purpose i/o/wake-up event 46/ smart card present detect #.. gpiow47/slp_sx# 53 diod8/di general purpose i/o/wake-up event 47 / chipset sleep state input #. table 6-5. general purpose i/o group 5 (set 5) signal pin # attribute description gpio50/clkrun# 124 diod8/diod8 general purpose i/o 50 / clock run #. gpio51/scclk 55 diod8/dod8 general purpose i/o 51 / smart card clock. gpio52/xstrb0/ jp6 34 diod8/do8 general purpose i/o 52 / x address strobe 0 / jp6. gpio53/lfckout 45 diod8/do8 general purpose i/o 53 / low frequency clock output. gpio54/vccfail 54 diod8/do8 general purpose i/o 54 / vcc failing. gpio55/scrst 9 diod8/dod8 general purpose i/o 55 / smart card reset. gpio56/scpwr 10 diod8/dod8 general purpose i/o 56 / smart card power fet control output #. gpio57/hfckout 13 diod8/do8 general purpose i/o 57 / high frequency clock output. table 6-6. general purpose i/o group 6 (set 6) signal pin # attribute description gpio60/xsrtb2/ jp4 32 diod8/do8 general purpose i/o 60 / x address strobe 2 / jp4. gpio61/xsrtb1/ jp5 33 diod8/do8 general purpose i/o 61 / x address strobe 1 / jp5. gpio62/scio 48 diod8/diod8 general purpose i/o 62 / smart card serial data i/o.
www.ite.com.tw IT8780F v0.3 23 power on strapping options 7. power on strapping options signal pin # description jp1 97 kbc_rtc_en (kbc and rtc enable) sampled at lreset# to determine the default values of kbc_en and rtc_en (bit0 of activation register, index 30h, of logical device 5 and 8). during lreset#, a week pull-up resistor will be turned on. 0: default values of kbc_en and rtc_en are 0. 1: default values of kbc_en and rtc_en are 1. jp2 98 reserved. during lreset#, do not be pulled to 0. jp3 100 conf_sel (configuration register base address select). sampled at lreset# to determine the base address of the configuration index/data register pair. during lreset#, a week pull-up resistor will be turned on. 0: 4eh/4fh. 1: 2eh/2fh. jp4 32 flash_rom_en (flash rom i/f enable) sampled at vsb power-on or lreset# to determine the default values of flash_seg1 , flash_seg2 and gpio2_3_sel . during lreset#, a week pull-down resistor will be turned on. 0: default values of flash_seg1 and flash_seg2 are 1. gpio2_3_sel is 0. 1: default values of flash_seg1 and flash_seg2 are 0. gpio2_3_sel is 1. jp5 33 add_mod_sel (x address 11-4 mode select) sampled at vsb power-on or lreset# to determine the default values of gpio1_sel and pin34_sel . during lreset#, a week pull-down resistor will be turned on. 0: default value of gpio1_sel is 1; default value of pin34_sel is 0. 1: default value of gpio1_sel is 0; default value of pin34_sel is 1. jp6 34 sb_add_sel (serial bus address select) sampled at vsb power-on or lreset# to determine the serial bus address. during lreset#, a week pull-down resistor will be turned on. 0: serial bus address is 0100111b. 1: serial bus address is 1010111b. atx power supply IT8780F pwbtin# (36) south bridge pwureq# (38) pson# (39) sio_wakeup slp_s5# (or slp_s3#) slp_sx# (53) pson# vcch system on/off button figure 7-1. IT8780F power control suggestion applications circuitry
www.ite.com.tw IT8780F v0.3 24
www.ite.com.tw IT8780F v0.3 25 configuration 8. configuration 8.1 configuring sequence description following the hardware reset or power-on reset, the IT8780F enters the normal mode with all logical devices disabled except kbc and rtc. the initial states (enable bits) of the logical devices (kbc and rtc) are determined by the state of pin 97 (jp1) at the raising edge of lreset# during power-on reset. there are three steps to completing the motherboard mode of configuration. step 1 is to enter the mb pnp mode. step 2 is to modify the data of configuration registers. step 3 is to exit the mb pnp mode. these three steps are explained below. please note that step three must be followed or an undefined state will occur. hardware reset wait for key string is the data "87h" ? mb pnp mode "87h"? y n any other i/o transition cycle i/o write to 2eh (or 4eh) y wait for next data any other i/o transition cycle i/o write to 2eh (or 4eh) n (1) enter the mb pnp mode to enter the mb pnp mode, 2 specific i/o write operations (87h) must be performed during the ?wait for key? state. the addresses of the configuration index/data register pair are determined by the power-on strapping of pin 100 (jp3). 2eh/2fh is selected when the power-on strapping value of this pin is low (without pull-up resistor); 4eh/4fh is selected when the power-on strapping value of this pin is high (with 10-kohm pull-up resistor).
www.ite.com.tw IT8780F v0.3 26 IT8780F (2) modifying the data of the registers all configuration registers can be accessed after the mb pnp mode is accessed. before a selected register is accessed, the content of index 07h must be changed to the ldn to which the register belongs, except some global registers. (3) exiting the mb pnp mode set bit 1 of the configure control register (index=02h) to ?1? to exit the mb pnp mode. 8.2 description of the configuration registers all the registers except apc/pme registers will be reset to the default state when reset is activated. table 8-1. global configuration registers ldn index r/w default configuration register or action all 02h wo na configure control all 07h r/w na logical device number (ldn) all 20h ro 87h chip id byte 1 all 21h ro 80h chip id byte 2 all 22h ro 00h chip version all 23h r/w ss0000s0b clock selection and flash rom i/f control register all 24h r/w s1000000b function fast disable register all 25h r/w 03h gpio set 4 multi-function pin selection register all 26h r/w 01100s00b gpio set 5 multi-function pin selection register all 27h r/w s00000ssb gpio set 6 and misc. multi-function pin selection register f4h note 2ah r/w 12h reserved register f4h note 2bh ro -- reserved register f4h note 2ch ro -- reserved register f4h note 2eh r/w 00h test 1 register f4h note 2fh r/w 00h test 2 register note: all these registers can be read from all ldns.
www.ite.com.tw IT8780F v0.3 27 configuration table 8-2. fdc configuration registers ldn index r/w default configuration register or action 00h 30h r/w 00h fdc activate 00h 60h r/w 03h fdc base address msb register 00h 61h r/w f0h fdc base address lsb register 00h 70h r/w 06h fdc interrupt level select 00h 74h r/w 02h fdc dma channel select 00h f0h r/w 00h fdc special configuration register 1 00h f1h r/w 00h fdc special configuration register 2 table 8-3. serial port 1 configuration registers ldn index r/w default configuration register or action 01h 30h r/w 00h serial port 1 activate 01h 60h r/w 03h serial port 1 base address msb register 01h 61h r/w f8h serial port 1 base address lsb register 01h 70h r/w 04h serial port 1 interrupt level select 01h f0h r/w 00h serial port 1 special configuration register table 8-4. serial port 2 configuration registers ldn index r/w default configuration register or action 02h 30h r/w 00h serial port 2 activate 02h 60h r/w 02h serial port 2 base address msb register 02h 61h r/w f8h serial port 2 base address lsb register 02h 70h r/w 03h serial port 2 interrupt level select 02h f0h r/w 00h serial port 2 special configuration register 1 02h f1h r/w 00h serial port 2 special configuration register 2 02h f2h r/w 7fh serial port 2 special configuration register 3 table 8-5. parallel port configuration registers ldn index r/w default configuration register or action 03h 30h r/w 00h parallel port activate 03h 60h r/w 03h parallel port primary base address msb register 03h 61h r/w 78h parallel port primary base address lsb register 03h 62h r/w 07h parallel port secondary base address msb register 03h 63h r/w 78h parallel port secondary base address lsb register 03h 64h r/w 00h post data port base address msb register 03h 65h r/w 80h post data port base address lsb register 03h 70h r/w 07h parallel port interrupt level select 03h 74h r/w 03h parallel port dma channel select note1 03h f0h r/w 03h note2 parallel port special configuration register
www.ite.com.tw IT8780F v0.3 28 IT8780F note 1: when the ecp mode is not enabled, this register is read only as ?04h?, and cannot be written. note 2: when bit 2 of the primary base address lsb register of parallel port is set to 1, the epp mode cannot be enabled. bit 0 of this register is always 0. table 8-7. swc and acpi configuration registers ldn index r/w power-well default configuration register or action 04h 30h r/w vsb 00h swc activate 04h 60h r/w vsb 00h pm1b_evt_blk base address msb register 04h 61h r/w vsb 00h pm1b_evt_blk base address lsb register 04h 62h r/w vsb 00h pm1b_cnt_blk base address msb register 04h 63h r/w vsb 00h pm1b_cnt_blk base address lsb register 04h 64h r/w vsb 00h gpe1_blk base address msb register 04h 65h r/w vsb 00h gpe1_blk base address lsb register 04h 70h r/w vsb 00h swc interrupt level select register 04h e0h r/w vsb 00h gpe1_sts_0 to irq enable register 04h e1h r/w vsb 00h gpe1_sts_1 to irq enable register 04h e2h r/w vsb 00h gpe1_sts_2 to irq enable register 04h e3h r/w vsb 00h gpe1_sts_3 to irq enable register 04h e4h r/w vsb 00h gpe1_sts_0 to smi# enable register 04h e5h r/w vsb 00h gpe1_sts_1 to smi# enable register 04h e6h r/w vsb 00h gpe1_sts_2 to smi# enable register 04h e7h r/w vsb 00h gpe1_sts_3 to smi# enable register 04h e8h ro vsb -- power on status register 04h f0h r/w vpp note 00h swc miscellaneous control register 04h f1h r/w vpp note 00h power on control register 04h f2h r/w vpp note 00h keyboard wake-up control register 04h f3h r/w vpp note 00h gpe1_sts_0 to pson# enable register 04h f4h r/w vpp note 00h gpe1_sts_1 to pson# enable register 04h f5h r/w vpp note 00h gpe1_sts_2 to pson# enable register 04h f6h r/w vpp note 00h gpe1_sts_3 to pson# enable register 04h f7h r/w vpp note 00h led control register 04h f8h r/w vpp note -- keyboard code data 0 register 04h f9h r/w vpp note -- keyboard code data 1 register 04h fah r/w vpp note -- keyboard code data 2 register 04h fbh r/w vpp note -- keyboard code data 3 register 04h fch r/w vpp note -- keyboard code data 4 register
www.ite.com.tw IT8780F v0.3 29 configuration table 8-8. swc and acpi configuration registers [cont?d] ldn index r/w power-well default configuration register or action 04h fdh r/w vpp note -- keyboard code data 5 register 04h feh r/w vpp note -- keyboard code data 6 register 04h ffh r/w vpp note -- keyboard code data 7 register note: vpp will be supported by vsb when vsb is present, and is supported by vbat when vsb is not present. its power well is the same as the rtc. table 8-9. keyboard configuration registers ldn index r/w default configuration register or action 05h 30h r/w 00h or 01h keyboard activate 05h 60h r/w 00h kbc data base address msb register 05h 61h r/w 60h kbc data base address lsb register 05h 62h r/w 00h kbc command base address msb register 05h 63h r/w 64h kbc command base address lsb register 05h 70h r/w 01h keyboard interrupt level select 05h 71h ro-r/w 02h keyboard interrupt type note 05h f0h r/w 00h kbc special configuration register note: the register is read only unless the write enable bit (index=f0h) is asserted. table 8-10. mouse configuration registers ldn index r/w default configuration register or action 06h 30h r/w 00h mouse activate 06h 70h r/w 0ch mouse interrupt level select 06h 71h ro-r/w 02h mouse interrupt type note 06h f0h r/w 00h mouse special configuration register note: the register is read only unless the write enable bit (index=f0h) is asserted.
www.ite.com.tw IT8780F v0.3 30 IT8780F table 8-12. gpio configuration registers ldn index r/w default configuration register or action 07h 60h r/w 00h programmable chip select 1 base address msb register 07h 61h r/w 00h programmable chip select 1 base address lsb register 07h 62h r/w 00h programmable chip select 2 base address msb register 07h 63h r/w 00h programmable chip select 2 base address lsb register 07h b0h r/w 00h gpiow set 1 pin polarity register 07h b1h r/w 00h gpio set 2 pin polarity register 07h b2h r/w 00h gpio set 3 pin polarity register 07h b3h r/w 00h gpiow set 4 pin polarity register 07h b4h r/w 00h gpio set 5 pin polarity register 07h b5h r/w 00h gpio set 6 pin polarity register 07h b8h r/w 00h gpiow set 1 pin internal pull-up enable register 07h b9h r/w 00h gpio set 2 pin internal pull-up enable register 07h bah r/w 00h gpio set 3 pin internal pull-up enable register 07h bbh r/w 00h gpiow set 4 pin internal pull-up enable register 07h bch r/w 00h gpio set 5 pin internal pull-up enable register 07h bdh r/w 00h gpio set 6 pin internal pull-up enable register 07h c0h r/w 00h simple i/o set 1 data register 07h c1h r/w 00h simple i/o set 2 data register 07h c2h r/w 00h simple i/o set 3 data register 07h c3h r/w 00h simple i/o set 4 data register 07h c4h r/w 00h simple i/o set 5 data register 07h c5h r/w 00h simple i/o set 6 data register 07h c8h r/w 00h simple i/o set 1 input/output selection register 07h c9h r/w 00h simple i/o set 2 input/output selection register 07h cah r/w 00h simple i/o set 3 input/output selection register 07h cbh r/w 00h simple i/o set 4 input/output selection register 07h cch r/w 00h simple i/o set 5 input/output selection register 07h cdh r/w 00h simple i/o set 6 input/output selection register 07h e3h r/w 00h irq3 external routing input pin mapping register 07h e4h r/w 00h irq4 external routing input pin mapping register 07h e5h r/w 00h irq5 external routing input pin mapping register 07h e6h r/w 00h irq6 external routing input pin mapping register
www.ite.com.tw IT8780F v0.3 31 configuration gpio configuration registers [cont?d] ldn index r/w default configuration register or action 07h e7h r/w 00h irq7 external routing input pin mapping register 07h e9h r/w 00h irq9 external routing input pin mapping register 07h eah r/w 00h irq10 external routing input pin mapping register 07h ebh r/w 00h irq11 external routing input pin mapping register 07h ech r/w 00h irq12 external routing input pin mapping register 07h eeh r/w 00h irq14 external routing input pin mapping register 07h efh r/w 00h irq15 external routing input pin mapping register 07h f0h r/w 00h programmable chip select configuration register 07h f1h r/w 00h user-defined memory base address high byte register 07h f2h r/w 00h user-defined memory base address low byte register 07h f3h r/w 00h user-defined memory size high byte register 07h f4h r/w 00h user-defined memory size low byte register table 8-13. rtc configuration registers ldn index r/w default configuration register or action 08h 30h r/w 00h or 01h rtc activate 08h 60h r/w 00h rtc primary base address msb register 08h 61h r/w 70h rtc primary base address lsb register 08h 62h r/w 00h rtc secondary base address msb register 08h 63h r/w 72h rtc secondary base address lsb register 08h 70h r/w 08h rtc interrupt level select 08h 71h ro-r/w 02h keyboard interrupt type note 08h f0h r/w 00h rtc special configuration register note: the register is read only unless the write enable bit (index=f0h) is asserted.
www.ite.com.tw IT8780F v0.3 32 IT8780F 8.3 global configuration registers (ldn: all) 8.3.1 configure control (index=02h) this register is write only . its values are not sticky; that is to say, a hardware reset will automatically clear the bits, and does not require the software to clear them. bit description 7-2 reserved 1 returns to the ?wait for key? state. this bit is used when the configuration sequence is completed. 0 resets all logical devices and restores configuration registers to their power-on states. 8.3.2 logical device number (ldn, index=07h) this register is used to select the current logical devices. by reading from or writing to the configuration of i/o, interrupt, dma and other special functions, all registers of the logical devices can be accessed. in addition, activate command is only effective for the selected logical devices. this register is read/write . 8.3.3 chip id byte 1 (index=20h, default=87h) this register is the chip id byte 1 and is read only . bits [7:0]=87h when read. 8.3.4 chip id byte 2 (index=21h, default=80h) this register is the chip id byte 2 and is read only . bits [7:0]=80h when read. 8.3.5 chip version (index=22h, default=00h) this register is the chip version and is read only .
www.ite.com.tw IT8780F v0.3 33 configuration 8.3.6 clock selection and flash rom i/f control register (index=23h, default=ss0000s0b, vsb) bit description 7 flash_seg1 (flash rom interface address segment 1 enable) this bit enables the flash rom interface address segment 1 (fffe_0000h-ffff_ffffh). the initial value of this bit depends on the vsb power-on strapping of pin 32 (jp4) (the initial value will be 1 if the strapping value of pin 32 is low). 0: disabled. 1: enable the flash rom interface address segment 1 (fffe_0000h-ffff_ffffh). 6 flash_seg2 (flash rom interface address segment 2 enable) this bit enables the flash rom interface address segment 2 (000f_0000h-000f_ffffh). the initial value of this bit depends on the vsb power-on strapping of pin 32 (jp4) (the initial value will be 1 if the strapping value of pin 32 is low). 0: disabled. 1: enable the flash rom interface address segment 2 (000f_0000h-000f_ffffh). 5 flash_seg3 (flash rom interface address segment 3 enable this bit enables the flash rom interface address segment 3 (000e_0000h-000e_ffffh). 0: disabled (default). 1: enable the flash rom interface address segment 3 (000e_0000h-000e_ffffh). 4 flash_seg4 (flash rom interface address segment 4 enable) this bit enables the flash rom interface address segment 4 (ffc0_0000h-fff7_ffffh). 0: disabled (default). 1: enable the flash rom interface address segment 4 (ffc0_0000h-fff7_ffffh). 3 flash_seg5 (flash rom interface address segment 5 enable) this bit enables the flash rom interface address segment 5 (fff8_0000h-fffd_ffffh). 0: disabled (default). 1: enable the flash rom interface address segment 5 (fff8_0000h-fffd_ffffh). 2 flash_we (flash rom interface write enable) this bit enables the flash rom interface write operation. 0: disabled (default). 1: enable the flash rom i/f write operation. 1 gpio1_sel (gpio set 1 multi-function pin selection) this bit selects the function of pin 1 ~ pin 8. the initial value of this bit depends on the vsb power-on strapping of pin 33 (jp5). 0: xa11~xa4. 1: gpiow10~gpiow17. 0 clkin_freq (clkin frequency) this bit determines the frequency of clkin pin. 0: 48 mhz (default). 1: 24 mhz.
www.ite.com.tw IT8780F v0.3 34 IT8780F 8.3.7 function fast disable register (index=24h, default=s1000000b, vsb) bit description 7 gpio2_3_sel (gpio set 2 and 3 multi-function pin selection) this bit selects the function of pins 14 ~ 19 and pins 23 ~ 31. the initial value of this bit depends on the vsb power-on strapping of pin 32. pin 14, pin 15, pins 16 ~ 19, pin 23, pins 24 ~31 0: xrd#, xwr#, xa3 ~ xa0, frcs#, xd7 ~ xd0 1: gpio20, gpio21, gpio22~gpio25, gpio27, gpio30~gpio37 6 pin22_sel (pin 22 multi-function selection). this bit selects the function of pin 22. 0: udmcs#. 1: gpio26 (default). 5 reserved 4 kbmsdis (keyboard and mouse controller disable) when set, this bit will force the keyboard and mouse controller function of IT8780F to be disabled regardless of the settings of their activation bits (bit 0 of ldn5 and ldn6 index 30h). 0: keyboard and mouse enable or disable, according to keyboard and mouse activation bits (default). 1: keyboard and mouse disable. 3 ppdis (parallel port disable) when set, this bit will force the parallel port function of IT8780F to be disabled regardless of the setting of its activation bit (bit 0 of ldn3 index 30h). 0: parallel port enable or disable, according to parallel port activation bit (default). 1: parallel port disable. 2 s2dis (serial port 2 disable) when set, this bit will force the serial port 2 function of IT8780F to be disabled regardless of the setting of its activation bit (bit 0 of ldn2 index 30h). 0: serial port 2 enable or disable, according to s2 activation bit (default). 1: serial port 2 disable. 1 s1dis (serial port 1 disable) when set, this bit will force the serial port 1 function of IT8780F to be disabled regardless of the setting of its activation bit (bit 0 of ldn1 index 30h). 0: serial port 1 enable or disable, according to s1 activation bit (default). 1: serial port 1 disable. 0 fdcdis (floppy disk controller disable) when set, this bit will force the floppy disk controller function of IT8780F to be disabled regardless of the setting of its activation bit (bit 0 of ldn0 index 30h). 0: fdc enable or disable, according to fdc activation bit (default). 1: fdc disable.
www.ite.com.tw IT8780F v0.3 35 configuration 8.3.8 gpio set 4 multi-function pin selection register (index=25h, default=03h, vsb) bit description 7 pin53_sel (pin 53 multi-function selection) this bit selects the function of pin 53. 0: slp_sx# (default). 1: gpiow47. 6 pin52_sel (pin 52 multi-function selection) this bit selects the function of pin 49. 0: scpsnt# (default). 1: gpiow46. 5 pin51_sel (pin 51 multi-function selection) this bit selects the function of pin 51. 0: led2 (default). 1: gpiow45. 4 pin50_sel (pin 50 multi-function selection) this bit selects the function of pin 50. 0: led1 (default) 1: gpiow44 3 pin49_sel (pin 49 multi-function selection) this bit selects the function of pin 49. 0: pwbtout (default). 1: gpiow43. 2 pin35_sel (pin 35 multi-function selection) this bit selects the function of pin 35. 0: slbtin# (default). 1: gpiow42. 1 pin21_sel (pin 21 multi-function selection) this bit selects the function of pin 21. 0: cs1#. 1: gpiow41 (default). 0 pin20_sel (pin 20 multi-function selection) this bit selects the function of pin 20. 0: cs2#. 1: gpiow40 (default).
www.ite.com.tw IT8780F v0.3 36 IT8780F 8.3.9 gpio set 5 multi-function pin selection register (index=26h, default= 01100s00b, vsb) bit description 7 pin13_sel (pin 13 multi-function selection) this bit selects the function of pin 13. 0: hfckout (default). 1: gpio57. 6 pin10_sel (pin 10 multi-function selection) this bit selects the function of pin 10. 0: scpwr. 1: gpio56 (default). 5 pin9_sel (pin 9 multi-function selection) this bit selects the function of pin 9. 0: scrst. 1: gpio55 (default). 4 pin54_sel (pin 54 multi-function selection) this bit selects the function of pin 54. 0: vccfail (default). 1: gpio54. 3 pin45_sel (pin 45 multi-function selection) this bit selects the function of pin 45. 0: lfckout (default). 1: gpio53. 2 pin34_sel (pin 34 multi-function selection) this bit selects the function of pin 34. the initial value of this bit depends on the vsb power-on strapping of pin 33. 0: xstrb0. 1: gpio52. 1 pin55_sel (pin 55 multi-function selection) this bit selects the function of pin 55. 0: scclk. (default). 1: gpio51. 0 pin124_sel (pin 124 multi-function selection) this bit selects the function of pin 124. 0: clkrun# (default). 1: gpio50.
www.ite.com.tw IT8780F v0.3 37 configuration 8.3.10 gpio set 6 and misc. multi-function pin selection register (index=27h, default= s00000ssb, vsb) bit description 7 sb_add (serial bus address) this bit selects the serial bus address. the initial value of this bit depends on the vsb power-on strapping of pin 34. 0: serial bus address is 0100111b. 1: serial bus address is 1010111b. 6 reserved 5 pin121_sel (pin 121 multi-function selection) this bit selects the function of pin 121. 0: ppdis (default). 1: kp12. 4 pin70_sel (pin 70 multi-function selection) this bit selects the function of pin 70. 0: drv1# (default). 1: kp16. 3 pin66_sel (pin 66 multi-function selection) this bit selects the function of pin 66. 0: mtr1# (default). 1: kp17. 2 pin48_sel (pin 48 multi-function selection) this bit selects the function of pin 48. 0: scio (default). 1: gpio62. 1 pin33_sel (pin 33 multi-function selection) this bit selects the function of pin 33. the initial value of this bit depends on the vsb power-on strapping of pin 32. 0: xstrb1. 1: gpio61. 0 pin32_sel (pin 32 multi-function selection) this bit selects the function of pin 32. the initial value of this bit depends on the vsb power-on strapping of pin 32. 0: xstrb2. 1: gpio60.
www.ite.com.tw IT8780F v0.3 38 IT8780F 8.3.11 reserved registers (index=2ah, 2bh and 2ch, default=00h, --, --) this is a protection register for ite test use. 8.3.12 test 1 register (index=2eh, default=00h) this register is the test 1 register and reserved for ite. it should not be set. 8.3.13 test 2 register (index=2fh, default=00h) this register is the test 2 register and reserved for ite. it should not be set. 8.4 fdc configuration registers (ldn=00h) 8.4.1 fdc activate (index=30h, default=00h) bit description 7-1 reserved 0 fdc_en (fdc activation) when fdcdis (bit 0 of the function fast disable register) is cleared and this bit is set, the fdc function is enabled. 0: disabled (default). 1: fdc enabled, if fdcdis=0. 8.4.2 fdc base address msb register (index=60h, default=03h) bit description 7-4 read only , with ?0h? for base addresses [15:12]. 3-0 mapped as base addresses [11:8]. 8.4.3 fdc base address lsb register (index=61h, default=f0h) bit description 7-3 read/write , mapped as base addresses [7:3]. 2-0 read only as ?000b.? 8.4.4 fdc interrupt level select (index=70h, default=06h) bit description 7-3 reserved with default ?0h.? 4 wk_en (wake-up enable) 0: disabled (default). 1: enable to set mod_irq_sts of gpe1_sts_3 by an activation of fdc irq. 3-0 select the interrupt level note1 for fdc. 8.4.5 fdc dma channel select (index=74h, default=02h) bit description 7-3 reserved with default ?00h.? 2-0 select the dma channel note2 for fdc.
www.ite.com.tw IT8780F v0.3 39 configuration 8.4.6 fdc special configuration register 1 (index=f0h, d7efault=00h) bit description 7-6 reserved with default ?00b?. 5 drvb_mod (floppy drive b operation mode). 0: drive b is pc-at mode (default). 1: drive b is 3-mode. 4 drva_mod (floppy drive a operation mode). 0: drive a is pc-at mode (default). 1: drive a is 3-mode. 3 fdc_irq_shr (fdc interrupt request sharing). 0: normal (default). 1: enable fdc irq sharing. 2 drv_swap (swap floppy drives). 0: normal (default). 1: swap floppy drives a, b. 1 reserved 0 soft_wp (software write protect). 0: normal (default). 1: software write protect. 8.4.7 fdc special configuration register 2 (index=f1h, default=00h) bit description 7-6 fdd b drive type select (dt1-0). 5-4 fdd a drive type select (dt1-0). 3-2 fdd b data rate table select (drt1-0). 1-0 fdd a data rate table select (drt1-0). 8.5 serial port 1 configuration registers (ldn=01h) 8.5.1 serial port 1 activate (index=30h, default=00h) bit description 7-1 reserved 0 s1_en (serial port 1 activation) when s1dis (bit 1 of the function fast disable register) is cleared and this bit is set, the serial port 1 function is enabled. 0: disabled (default). 1: serial port 1 enabled, if s1dis=0. 8.5.2 serial port 1 base address msb register (index=60h, default=03h) bit description 7-4 read only as ?0h? for base addresses [15:12]. 3-0 read/write , mapped as base addresses [11:8].
www.ite.com.tw IT8780F v0.3 40 IT8780F 8.5.3 serial port 1 base address lsb register (index=61h, default=f8h) bit description 7-3 read/write , mapped as base addresses [7:3]. 2-0 read only as ?000b.? 8.5.4 serial port 1 interrupt level select (index=70h, default=04h) bit description 7-5 reserved with default ?0h.? 4 wk_en (wake-up enable) 0: disable (default). 1: enable to set mod_irq_sts of gpe1_sts_3 by an activation of serial port 1 irq. 3-0 select the interrupt level note1 for serial port 1. 8.5.5 serial port 1 special configuration register (index=f0h, default=00h) bit description 7-2 reserved 1 s1_clk (serial port 1 clock source) 0: 24mhz/13 (default). 1: 24mhz. 0 s1_irq_shr (serial port 1 interrupt request sharing) 0: normal (default). 1: enable s1 irq sharing. 8.6 serial port 2 configuration registers (ldn=02h) 8.6.1 serial port 2 activate (index=30h, default=00h) bit description 7-1 reserved 0 s2_en (serial port 2 activation) when s2dis (bit 2 of the function fast disable register) is cleared and this bit is set, the serial port 2 function is enabled. 0: disabled (default). 1: serial port 2 enabled, if s2dis=0. 8.6.2 serial port 2 base address msb register (index=60h, default=02h) bit description 7-4 read only with ?0h? for base addresses [15:12]. 3-0 read/write , mapped as base addresses [11:8]. 8.6.3 serial port 2 base address lsb register (index=61h, default=f8h) bit description 7-3 read/write , mapped as base addresses [7:3]. 2-0 read only as ?000b.?
www.ite.com.tw IT8780F v0.3 41 configuration 8.6.4 serial port 2 interrupt level select (index=70h, default=03h) bit description 7-5 reserved with default ?0h.? 4 wk_en (wake-up enable) 0: disabled (default). 1: enable to set mod_irq_sts of gpe1_sts_3 by an activation of serial port 2 irq. 3-0 select the interrupt level note1 for serial port 2. 8.6.5 serial port 2 special configuration register 1 (index=f0h, default=00h) bit description 7-6 s2_mod (serial port 2 mode) 00: standard (default) 01: smart card reader (scr) else: reserved 5-2 reserved with default ?0.h? 1 s2_clk (serial port 2 clock source) 0: 24mhz/13 (default). 1: 24mhz. 0 s2_irq_shr (serial port 2 interrupt request sharing) 0: normal (default). 1: enable s2 irq sharing. 8.6.6 serial port 2 special configuration register 2 (index=f1h, default=00h) this register is valid only when serial port 2?s mode is smart card reader. bit description 7-3 reserved 2 scpwr_por (scpwr polarity) 0: active low (default). 1: active high. 1-0 scclk_sel1-0 (scclk frequency selection) 00: stop (default) 01: 3.5 mhz 10: 7.1 mhz 11: special frequency (96 mhz/scdiv) 8.6.7 serial port 2 special configuration register 3 (index=f2h, default=7fh) this register is valid only when serial port 2?s mode is smart card reader. bit description 7 reserved 6-0 scdiv6-0 (scclk special divisor).
www.ite.com.tw IT8780F v0.3 42 IT8780F 8.7 parallel port configuration registers (ldn=03h) 8.7.1 parallel port activate (index=30h, default=00h) bit description 7-1 reserved 0 pp_en (parallel port activation) when ppdis (bit 3 of the function fast disable register) is cleared and this bit is set, the parallel port function is enabled. 0: disabled (default). 1: parallel port enabled, if ppdis=0. 8.7.2 parallel port primary base address msb register (index=60h, default=03h) bit description 7-4 read only as ?0h? for base addresses [15:12]. 3-0 read/write , mapped as base addresses [11:8]. 8.7.3 parallel port primary base address lsb register (index=61h, default=78h) if the bit 2 is set to 1, the epp mode is disabled automatically. bit description 7-2 read/write , mapped as base addresses [7:2]. 1-0 read only as ?00b.? 8.7.4 parallel port secondary base address msb register (index=62h, default=07h) bit description 7-4 read only as ?0h? for base addresses [15:12]. 3-0 read/write , mapped as base addresses [11:8]. 8.7.5 parallel port secondary base address lsb register (index=63h, default=78h) bit description 7-2 read/write , mapped as base addresses [7:2]. 1-0 read only as ?00b.? 8.7.6 post data port base address msb register (index=64h, default=00h) bit description 7-4 read only as ?0h? for base addresses [15:12]. 3-0 read/write , mapped as base addresses [11:8]. 8.7.7 post data port base address lsb register (index=65h, default=80h) bit description 7-2 read/write , mapped as base addresses [7:2]. 1-0 read only as ?00b.?
www.ite.com.tw IT8780F v0.3 43 configuration 8.7.8 parallel port interrupt level select (index =70h, default=07h) bit description 7-5 reserved with default ?0h.? 4 wk_en (wake-up enable) 0: disabled (default). 1: enable to set mod_irq_sts of gpe1_sts_3 by an activation of parallel port irq. 3-0 select the interrupt level note1 for parallel port. 8.7.9 parallel port dma channel select (index=74h, default=03h) bit description 7-3 reserved with default ?00h.? 2-0 select the dma channel note2 for parallel port. 8.7.10 parallel port special configuration register (index=f0h, default=03h) bit description 7-4 reserved 3 postdis (post data port disable) when this bit is set, the post data port is disabled. it is better to disable the post data port after the system is boot up. 0: post data port enable (default). 1: post data port disable. 2 pp_irq_shr (parallel port interrupt request sharing) 0: normal (default). 1: enable parallel port irq sharing. 1-0 parallel port modes 00: standard parallel port mode (spp) 01: epp mode 10: ecp mode 11: epp mode & ecp mode (default) if bit 1 is set, ecp mode is enabled. if bit 0 is set, epp mode is enabled. these two bits are independent. however, according to the epp spec., when parallel port primary base address lsb register bit 2 is set to 1, the epp mode cannot be enabled. 8.8 swc and acpi configuration registers (ldn=04h) 8.8.1 swc activate register (index=30h, default=00h) bit description 7-1 reserved 0 swc_en (swc module activation) 0: disabled (default). 1: swc enabled. 8.8.2 pm1b_evt_blk base address msb register (index=60h, default=00h) bit description 7-4 read only as ?0h? for base addresses [15:12]. 3-0 read/write , mapped as base addresses [11:8].
www.ite.com.tw IT8780F v0.3 44 IT8780F 8.8.3 pm1b_evt_blk base address lsb register (index=61h, default=00h) bit description 7-2 read/write , mapped as base addresses [7:2]. 1-0 read only as ?00b.? 8.8.4 pm1b_cnt_blk base address msb register (index=62h, default=00h) bit description 7-4 read only as ?0h? for base addresses [15:12]. 3-0 read/write , mapped as base addresses [11:8]. 8.8.5 pm1b_cnt_blk base address lsb register (index=63h, default=00h) bit description 7-1 read/write , mapped as base addresses [7:1]. 0 read only as ?0b.? 8.8.6 gpe1_blk base address msb register (index=64h, default=00h) bit description 7-4 read only as ?0h? for base addresses [15:12]. 3-0 read/write , mapped as base addresses [11:8]. 8.8.7 gpe1_blk base address lsb register (index=65h, default=00h) bit description 7-3 read/write , mapped as base addresses [7:3]. 2-0 read only as ?000b.? 8.8.8 swc interrupt level select (index=70h, default=00h) bit description 7-4 reserved with default ?0h.? 3-0 select the interrupt level note1 for swc. 8.8.9 gpe1_sts_0 to irq enable register (ge0_2irq) (index=e0h, default=00h) bit description 7 ge0_2irq7 enable the activation of the irq by an active event of gpiow17_sts. the event affects the output regardless of the setting of the gpe1_en_0 register. 0: disabled (default). 1: enabled. 6-0 ge0_2pon6-0. these bits are the same as above for gpiow16_sts to gpiow10_sts.
www.ite.com.tw IT8780F v0.3 45 configuration 8.8.10 gpe1_sts_1 to irq enable register (ge1_2irq) (index=e1h, default=00h) bit description 7 ge1_2irq7 enable the activation of the irq by an active event of gpiow47_sts. the event affects the output regardless of the setting of the gpe1_en_1 register. 0: disabled (default). 1: enabled. 6-0 ge1_2irq6-0. these bits are the same as above for gpiow46_sts to gpiow40_sts. 8.8.11 gpe1_sts_2 to irq enable register (ge2_2irq) (index=e2h, default=00h) bit description 7 ge2_2irq7 enable the activation of the irq by an active event of pbt_evt_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disabled (default). 1: enabled. 6 ge2_2irq6 enable the activation of the irq by an active event of sbt_evt_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disabled (default). 1: enabled. 5 ge2_2irq5 enable the activation of the irq by an active event of kbd_evt3_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disabled (default). 1: enabled. 4 ge2_2irq4 enable the activation of the irq by an active event of kbd_evt2_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disabled (default). 1: enabled. 3 ge2_2irq3 enable the activation of the irq by an active event of kbd_evt1_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disabled (default). 1: enabled. 2 ge2_2irq2 enable the activation of the irq by an active event of ms_evt_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disabled (default). 1: enabled. 1 ge2_2irq1 enable the activation of the irq by an active event of ri2_evt_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disabled (default). 1: enabled. 0 ge2_2irq0 enable the activation of the irq by an active event of ri1_evt_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disabled (default). 1: enabled.
www.ite.com.tw IT8780F v0.3 46 IT8780F 8.8.12 gpe1_sts_3 to irq enable register (ge3_2irq) (index=e3h, default=00h) bit description 7 ge3_2irq7 enable the de-activation of the irq by an active event of sw_off_sts. the event affects the output regardless of the setting of the gpe1_en_3 register. 0: disabled (default). 1: enabled. 6 ge3_2irq6 enable the activation of the irq by an active event of sw_on_sts. the event affects the output regardless of the setting of the gpe1_en_3 register. 0: disabled (default). 1: enabled. 5 reserved 4 ge3_2irq4 enable the activation of the irq by an active event of mod_irq_sts. the event affects the output regardless of the setting of the gpe1_en_3 register. 0: disabled (default). 1: enabled. 3 ge3_2irq3 enable the activation of the irq by an active event of ms_irq_sts. the event affects the output regardless of the setting of the gpe1_en_3 register. 0: disabled (default). 1: enable. 2 ge3_2irq2 enable the activation of the irq by an active event of kbd_irq_sts. the event affects the output regardless of the setting of the gpe1_en_3 register. 0: disable (default). 1: enabled. 1 ge3_2irq1 enable the activation of the irq by an active event of p12_evt_sts. the event affects the output regardless of the setting of the gpe1_en_3 register. 0: disabled (default). 1: enabled. 0 ge3_2irq0 enable the activation of the irq by an active event of rtc_evt_sts. the event affects the output regardless of the setting of the gpe1_en_3 register. 0: disabled (default). 1: enabled. 8.8.13 gpe1_sts_0 to smi# enable register (ge0_2smi) (index=e4h, default=00h) bit description 7 ge0_2smi7 enable the activation of the smi# by an active event of gpiow17_sts. the event affects the output regardless of the setting of the gpe1_en_0 register. 0: disabled (default). 1: enabled. 6-0 ge0_2pon6-0 these bits are the same as above for gpiow16_sts to gpiow10_sts.
www.ite.com.tw IT8780F v0.3 47 configuration 8.8.14 gpe1_sts_1 to smi# enable register (ge1_2smi) (index=e5h, default=00h) bit description 7 ge1_2smi7 enable the activation of the smi# by an active event of gpiow47_sts. the event affects the output regardless of the setting of the gpe1_en_1 register. 0: disabled (default). 1: enabled. 6-0 ge1_2smi6-0 these bits are the same as above for gpiow46_sts to gpiow40_sts. 8.8.15 gpe1_sts_2 to smi# enable register (ge1_2smi) (index=e6h, default=00h) bit description 7 ge2_2smi7 enable the activation of the smi# by an active event of pbt_evt_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disabled (default). 1: enabled. 6 ge2_2smi6 enable the activation of the smi# by an active event of sbt_evt_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disable (default). 1: enable. 5 ge2_2smi5 enable the activation of the smi# by an active event of kbd_evt3_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disable (default). 1: enable. 4 ge2_2smi4 enable the activation of the smi# by an active event of kbd_evt2_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disabled (default). 1: enabled. 3 ge2_2smi3 enable the activation of the smi# by an active event of kbd_evt1_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disabled (default). 1: enabled. 2 ge2_2smi2 enable the activation of the smi# by an active event of ms_evt_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disabled (default). 1: enabled. 1 ge2_2smi1 enable the activation of the smi# by an active event of ri2_evt_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disabled (default). 1: enabled. 0 ge2_2smi0 enable the activation of the smi# by an active event of ri1_evt_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disabled (default). 1: enabled.
www.ite.com.tw IT8780F v0.3 48 IT8780F 8.8.16 gpe1_sts_3 to smi# enable register (ge3_2smi) (index=e7h, default=00h) bit description 7 ge3_2smi7 enable the de-activation of the smi# by an active event of sw_off_sts. the event affects the output regardless of the setting of the gpe1_en_3 register. 0: disabled (default). 1: enabled. 6 ge3_2smi6 enable the activation of the smi# by an active event of sw_on_sts. the event affects the output regardless of the setting of the gpe1_en_3 register. 0: disabled (default). 1: enabled. 5 reserved 4 ge3_2smi4 enable the activation of the smi# by an active event of mod_irq_sts. the event affects the output regardless of the setting of the gpe1_en_3 register. 0: disabled (default). 1: enabled. 3 ge3_2smi3 enable the activation of the smi# by an active event of ms_irq_sts. the event affects the output regardless of the setting of the gpe1_en_3 register. 0: disabled (default). 1: enabled. 2 ge3_2smi2 enable the activation of the smi# by an active event of kbd_irq_sts. the event affects the output regardless of the setting of the gpe1_en_3 register. 0: disabled (default). 1: enabled. 1 ge3_2smi1 enable the activation of the smi# by an active event of p12_evt_sts. the event affects the output regardless of the setting of the gpe1_en_3 register. 0: disabled (default). 1: enabled. 0 ge3_2smi0 enable the activation of the smi# by an active event of rtc_evt_sts. the event affects the output regardless of the setting of the gpe1_en_3 register. 0: disabled (default). 1: enabled.
www.ite.com.tw IT8780F v0.3 49 configuration 8.8.17 power on status register (ponsts) (index=e8h, default=--) bit r/w description 7 r/w1c pwr_fail (power fail status) indicate that IT8780F has been waken-up from a power fail condition (both vcc and vsb off). this bit is set by the vsb power-on reset. writing ?1? will clear it; writing ?0? will be ignored. 0: inactive. 1: waken-up from power fail. 6 ro last_pson (last value of pson) this bit reflects the last value of the pson# pin when the last previous power fail condition (both vcc and vsb off) occurred. writing to this bit is ignored. 0: pson# inactive -- vcc power off (default). 1: pson# active ? vcc power on. 5-0 r/w reserved 8.8.18 swc miscellaneous control register (swc_ctl) (index=f0h, default=00h) bit r/w description 7 r/w sw_off_ctl (software off control) write ?1? to set the sw_off_sts bit in the gpe1_sts_3 register, which triggers a vcc power off sequence. this bit clears itself. 0: inactive (default). 1: trigger a vcc power off sequence. 6 r/w sw_on_ctl (software on control) write ?1? to set the sw_on_sts bit in the gpe1_sts_3 register, which triggers a vcc power on sequence. this bit clears itself. when the vcc power is off, this bit can be written only through the sm bus. 0: inactive (default). 1: trigger a vcc power on sequence. 5 r/w1c pbt_ovr_sts (power button override status) indicate that the power button override event has occurred (power button pressed for more than 4 seconds). in this condition, the vcc power is unconditionally turned off. writing ?1? will clear this bit; writing ?0? will be ignored. 0: inactive (default). 1: power button override event has occurred. 4 r/w dis_asw_kbms (disable auto-swap keyboard and mouse inputs) disable the hardware auto-swapping keyboard (kclk, kdat) and mouse (mclk, mdat) signals. the auto-swap function is only enabled in both dis_asw_kbms and swap_kbms being cleared. 0: enable hardware auto-swapping keyboard and mouse inputs (default). 1: disable hardware auto-swapping keyboard and mouse inputs. 3 r/w swap_kbms (swap keyboard and mouse inputs) when this bit set, the keyboard signals (kclk, kdat) will be swapped by mouse signals (mclk, mdat), and the auto-swap function is disabled regardless of the setting of dis_asw_kbms. 0: no forced swapping (default). 1: swaps the keyboard and mouse signals. 2 r/w en_rtc_evt (enable rtc alarm event) enable the rtc alarm event to the pm1b_sts_high and to the pm1b_en_high registers. however, the rtc_evt_sts bit in the gpe1_sts_3 register and the rtc_evt_en bit in the gpe1_en_3 register are not affected. 0: disable the rtc alarm event (default). 1: enable the rtc alarm event.
www.ite.com.tw IT8780F v0.3 50 IT8780F [cont?d] bit r/w description 1 r/w en_slpbtn_evt (enable sleep button event) enable the sleep button pressing event to the pm1b_sts_high and to the pm1b_en_high registers. however, the slpt_evt_sts bit in the gpe1_sts_2 register and the slbt_evt_en bit in the gpe1_en_2 register are not affected. 0: disable the sleep button pressing event (default). 1: enable the sleep button pressing event. 0 r/w en_pwrbtn_evt (enable power button event) enable the power button pressing event to the pm1b_sts_high and to the pm1b_en_high registers. however, the pwrt_evt_sts bit in the gpe1_sts_2 register and the pwrt_evt_en bit in the gpe1_en_2 register are not affected. 0: disable the power button pressing event (default). 1: enable the power button pressing event. 8.8.19 power on control register (ponctl) (index=f1h, default=00h, vpp) bit r/w description 7 r/w gpiow1_deb (gpiow1 de-bounce control) this bit controls the de-bounced mode of gpiow17-10. if the fast mode is selected, the gpiow17_sts-gpiow10_sts will not be active unless the related inputs have been active for at least 800ns. if the slow mode is selected, the gpiow17_sts- gpiow10_sts will not be active unless the related inputs have been active for at least 8ms. 0: fast mode (default). 1: slow mode. 6 r/w gpiow4_deb (gpiow4 de-bounce control) this bit controls the de-bounced mode of gpiow47-40. if the fast mode is selected, the gpiow47_sts-gpiow40_sts will not be active unless the related inputs have been active for at least 800ns. if the slow mode is selected, the gpiow47_sts- gpiow40_sts will not be active unless the related inputs have been active for at least 8ms. 0: fast mode (default). 1: slow mode. 5-4 r/w rsu_mod1-0 (resume mode control) these bits control the behavior of the pson# and pwureq# signals after waking-up from a power fail condition (both vcc and vsb are off). shows the details. 3 r/w slp_sx_2pson (slp_sx# signal to pson#) enable slp_sx# signal as a source to activate pson#. 0: disabled (default). 1: enable pson# from slp_sx# signal. 2-0 r/w msevcfg2-0 (mouse event configuration) these bits configure the mouse data sequence for the mouse event. before setting them to a new value, these bits should be cleared by writing a value of 000b. 000: disable mouse wake-up detection (default) 001: wake-up on any mouse movement or button click 010: wake-up on left button click 011: wake-up on left button double-click 100: wake-up on right button click 101: wake-up on right button double-click 110: wake-up on any button single-click 111: wake-up on any button double-click
www.ite.com.tw IT8780F v0.3 51 configuration table 8-15. pson# and pwureq# as a function of the resume mode. rsu_mod1-0 slp_sx# 1 last_pson rtc alarm in power fail pson# pwureq# 0 x x inactive -- 00 1 x x active pulse 0 x 0 inactive -- 1 x x active pulse 01 x x 1 active pulse x 0 x inactive -- 10 x 1 x active pulse x 0 0 inactive -- x 1 x active pulse 11 x x 1 active pulse 1. slp_sx_2pson should be set or slp_sx# will not affect pson#. 8.8.20 keyboard wake-up control register (kbd_ctl) (index=f2h, default=00h, vpp) bit description 7 kbd_mod (keyboard wake-up mode control) this bit selects the keyboard wake-up modes for the keyboard wake-up detector. 0: ?power management keys? mode (default). 1: ?password? mode. 6-5 evt3cfg1-0 (keyboard event 3 configuration) these bits configure the keyboard data sequence for keyboard event 3, which indicates that ?pm key 3? was pressed on the keyboard. they are relevant only if kbd_mod=0. the keyboard data sequence used to detect keyboard event 3 is stored in registers keycd0-2, starting with keycd0. 00: 0 byte ? keyboard event 3 disabled (default) 01: 1 byte (keycd0) 10: 2 bytes (keycd0, keycd1) 11: 3 bytes (keycd0, keycd1, keycd2) 4-3 evt2cfg1-0 (keyboard event 2 configuration) these bits configure the keyboard data sequence for keyboard event 2, which indicates that ?pm key 2? was pressed on the keyboard. they are relevant only if kbd_mod=0. the keyboard data sequence used to detect keyboard event 2 is stored in registers keycd3-5, starting with keycd3. 00: 0 byte ? keyboard event 2 disabled (default) 01: 1 byte (keycd3) 10: 2 bytes (keycd3, keycd4) 11: 3 bytes (keycd3, keycd4, keycd5)
www.ite.com.tw IT8780F v0.3 52 IT8780F keyboard wake-up control register [cont?d] bit description 2-0 evt1cfg2-0 (keyboard event configuration) these bits configure the keyboard data sequence for keyboard event 1, which indicates that ?pm key 1? or ?password? was pressed on the keyboard. if kbd_mod=1 (?password? mode). evt1cfg2-0 bits determine the keys? number. the keyboard data sequence used to detect a keyboard event is stored in registers keycd0-7, starting with keycd0. if kbd_mod=0 (?power management keys? mode), evt1cfg2-0 determine the byte number. the keyboard data sequence used to detect keyboard event 2 is stored in registers keycd6-7, starting with keycd6. kbd_mod=0: 000: 0 byte ? keyboard event 1 disabled (default) 001: 1 byte (keycd6) 010: 2 bytes (keycd6, keycd7) 100: any key mode others: reserved kbd_mod=1: 000~111: ?password? mode with 1~8 keys ?make? code (excluding shift, enter, back space, and alt keys) 8.8.21 gpe1_sts_0 to pson# enable register (ge0_2pon) (index=f3h, default=00h, vpp) bit description 7 ge0_2pon7 enable the activation (turn vcc on) of the pson# by an active event of gpiow17_sts. the event affects the output regardless of the setting of the gpe1_en_0 register. 0: disabled (default). 1: enabled. 6-0 ge0_2pon6-0 these bits are the same as above for gpiow16_sts to gpiow10_sts. 8.8.22 gpe1_sts_1 to pson# enable register (ge1_2pon) (index=f4h, default=00h, vpp) bit description 7 ge1_2pon7 enable the activation (turn vcc on) of the pson# by an active event of gpiow47_sts. the event affects the output regardless of the setting of the gpe1_en_1 register. 0: disabled (default). 1: enabled. 6-0 ge1_2pon6-0 these bits are the same as above for gpiow46_sts to gpiow40_sts.
www.ite.com.tw IT8780F v0.3 53 configuration 8.8.23 gpe1_sts_2 to pson# enable register (ge1_2pon) (index=f5h, default=00h, vpp) bit description 7 reserved pressing power button will always cause the activation (turn vcc on) of the pson# signal. 6 ge2_2pon6 enable the activation (turn vcc on) of the pson# by an active event of sbt_evt_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disabled (default). 1: enabled. 5 ge2_2pon5 enable the activation (turn vcc on) of the pson# by an active event of kbd_evt3_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disabled (default). 1: enabled. 4 ge2_2pon4 enable the activation (turn vcc on) of the pson# by an active event of kbd_evt2_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disabled (default). 1: enabled. 3 ge2_2pon3 enable the activation (turn vcc on) of the pson# by an active event of kbd_evt1_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disable (default). 1: enable. 2 ge2_2pon2 enable the activation (turn vcc on) of the pson# by an active event of ms_evt_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disabled (default). 1: enabled. 1 ge2_2pon1 enable the activation (turn vcc on) of the pson# by an active event of ri2_evt_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disabled (default). 1: enabled. 0 ge2_2pon0 enable the activation (turn vcc on) of the pson# by an active event of ri1_evt_sts. the event affects the output regardless of the setting of the gpe1_en_2 register. 0: disabled (default). 1: enabled.
www.ite.com.tw IT8780F v0.3 54 IT8780F 8.8.24 gpe1_sts_3 to pson# enable register (ge3_2pon) (index=f6h, default=00h, vpp) bit description 7 ge3_2pon7 enable the de-activation (turn vcc off ) of the pson# by an active event of sw_off_sts. the event affects the output regardless of the setting of the gpe1_en_3 register. 0: disabled (default). 1: enabled. 6 ge3_2pon6 enable the activation (turn vcc on) of the pson# by an active event of sw_on_sts. the event affects the output regardless of the setting of the gpe1_en_3 register. 0: disabled (default). 1: enabled. 5 reserved 4 reserved 3 reserved 2 reserved 1 reserved 0 ge3_2pon0 enable the activation (turn vcc on) of the pson# by an active event of rtc_evt_sts. the event affects the output regardless of the setting of the gpe1_en_3 register. 0: disabled (default). 1: enabled. 8.8.25 led control register (led_ctl) (index=f7h, default=00h, vpp) bit description 7 reserved 6 ledpol ( polarity of leds) this bit determines the polarity of led1 and led2 outputs. when this bit is set to 0, the led1 and led2 is active low to turn on the led. when this bit is set to 1, the led1 and led2 are active high to turn on the led. 0: active low (default). 1: active high. 5 led2_onvsb (led2 operation mode when vsb only) this bit determines the operation mode of led2 when vsb is on and vcc is off. 0: off (default). 1: blinking on 1/4 hz with 12.25% duty cycle. 4-3 led2blk1-0 (led1 blink rate) these bits control the blinking rate of led2 output when power is on. bits1-0 rate(hz) duty cycle 00 off always inactive (default) 01 0.25 12.25% 10 1 50% 11 on always active 2 led1_onvsb (led1 operation mode when vsb only) this bit determines the operation mode of led1 when vsb is on and vcc is off. 0: off (default). 1: blinking on 1/4 hz with 12.25% duty cycle.
www.ite.com.tw IT8780F v0.3 55 configuration led control register [cont?d] bit description 1-0 led1blk1-0 (led1 blink rate) these bits control the blinking rate of led1 output when power is on. bits1-0 rate (hz) duty cycle 00 off always inactive (default) 01 0.25 12.25% 10 1 50% 11 on always active 8.8.26 keyboard code data 0-7 registers (keycd0-7) (index=f8h-ffh, default = -- ,vpp) bit description 7-0 keyboard scan code data 7-0. 8.9 keyboard configuration registers (ldn=05h) 8.9.1 keyboard activate (index=30h, default=01h or 00h) bit description 7-1 reserved 0 kbd_en (keyboard activation) when kbcdis (bit 4 of the function fast disable register) is cleared and this bit is set, the keyboard function is enabled. the default value depends on the state of the rts1# when lreset# is activated. the default value is 1b for the high state of rts1# when lreset# is activated. it is 0b for the low state of rts1# when lreset# is activated. 0: disabled. 1: keyboard enabled, if kbcdis=0. 8.9.2 kbc data base address msb register (index=60h, default=00h) bit description 7-4 read only as ?0h? for base addresses [15:12]. 3-0 read/write, mapped as base addresses [11:8]. 8.9.3 kbc data base address lsb register (index=61h, default=60h) bit description 7-0 read/write , mapped as base addresses [7:0]. 8.9.4 kbc command base address msb register (index=62h, default=00h) bit description 7-4 read only as ?0h? for base addresses [15:12]. 3-0 read/write , mapped as base addresses [11:8]. 8.9.5 kbc command base address lsb register (index=63h, default=64h) bit description 7-0 read/write , mapped as base addresses [7:0].
www.ite.com.tw IT8780F v0.3 56 IT8780F 8.9.6 keyboard interrupt level select (index=70h, default=01h) bit description 7-5 reserved with default ?0h.? 4 wk_en (wake-up enable) 0: disabled (default). 1: enable to set kbd_irq_sts of gpe_sts_3 by an activation of kbd_irq. 3-0 select the interrupt level note1 for keyboard. 8.9.7 keyboard interrupt type (index=71h, default=02h) this register indicates the type of interrupt set for keyboard and is read only as ?02h? when bit 0 of the keyboard special configuration register is cleared. when bit 0 is set, this type of interrupt can be selected as level or edge trigger. bit description 7-2 reserved 1 act_level (active level) 0: low level. 1: high level (default). 0 act_type (active type) 0: edge type. 1: level type. 8.9.8 kbc special configuration register (index=f0h, default=00h) bit description 7-5 reserved 4 kbd_irq_shr (keyboard interrupt request sharing) 0: normal (default). 1: enable keyboard irq sharing. 3 kbc_clk (kbc clock frequency selection) 0: kbc?s clock frequency is 12 mhz (default). 1: kbc?s clock frequency is 8 mhz. 2 reserved 1 irq_type_wr (interrupt type register write enable) 0: type of interrupt of keyboard is fixed (default). 1: type of interrupt of keyboard can be changed. 0 ext_rom (external rom for microprocessor) 0: internal built-in rom is used (default). 1: enable the external access rom of 8042. 8.10 mouse configuration registers (ldn=06h) 8.10.1 mouse activate (index=30h, default=00h) bit description 7-1 reserved 0 ms_en (mouse activation) when the keyboard function is enabled, setting this bit will enable the mouse function. 0: disabled (default). 1: mouse enabled, if keyboard is enabled.
www.ite.com.tw IT8780F v0.3 57 configuration 8.10.2 mouse interrupt level select (index=70h, default=0ch) bit description 7-4 reserved with default ?0h.? 3-0 select the interrupt level note1 for mouse. 8.10.3 mouse interrupt type (index=71h, default=02h) this register indicates the type of interrupt used for mouse and is read only as ?02h? when bit 0 of the mouse special configuration register is cleared. when bit 0 is set, the type of interrupt can be selected as level or edge trigger. bit description 7-2 reserved 1 act_level (active level) 0: low level. 1: high level (default). 0 act_type (active type) 0: edge type. 1: level type. 8.10.4 mouse special configuration register (index=f0h, default=00h) bit description 7-2 reserved with default ?00h.? 1 ms_irq_shr (keyboard interrupt request sharing) 0: normal (default). 1: enable keyboard irq sharing. 0 irq_type_wr (interrupt type register write enable) 0: type of interrupt of mouse is fixed (default). 1: type of interrupt of mouse can be changed. 8.11 gpio configuration registers (ldn=07h) 8.11.1 programmable chip select 1 base address msb register (index=60h, default=00h) bit description 7-4 read only as ?0h? for base addresses [15:12]. 3-0 read/write , mapped as base addresses [11:8]. 8.11.2 programmable chip select 1 base address lsb register (index=61h, default=00h) bit description 7-0 read/write , mapped as base addresses [7:0]. 8.11.3 programmable chip select 2 base address msb register (index=62h, default=00h) bit description 7-4 read only as ?0h? for base addresses [15:12]. 3-0 read/write , mapped as base addresses [11:8].
www.ite.com.tw IT8780F v0.3 58 IT8780F 8.11.4 programmable chip select 2 base address lsb register (index=63h, default=00h) bit description 7-0 read/write , mapped as base addresses [7:0]. 8.11.5 gpio(w) set 1, 2, 3, 4, 5, and 6 pin polarity registers (index=b0h, b1h, b2h, b3h, b4h, and b5h, default=00h) bit description 7-0 pin_por7-0 (pin polarity) these bits program the gpio pins? polarity. 0: non-inverting (default). 1: inverting. 8.11.6 gpio(w) set 1, 2, 3, 4, 5, and 6 pin internal pull-up enable registers (index=b8h, b9h, bah, bbh, bch, and bdh, default=00h) bit description 7-0 pin_pu7-0 (pin pull-up) these bits are used to enable the gpio pin internal pull-up. 0: no pull-up (default). 1: with pull-up resistor. 8.11.7 simple i/o set 1, 2, 3, 4, 5, and 6 data registers (index=c0h, c1h, c2h, c3h, c4h, and c5h, default=00h) bit description 7-0 gpio_d7-0 (general purpose i/o data) these bits are the data registers of the gpio pins. when the gpio pin is set as input mode, the register is read-only and reflects the state of the pin. when the gpio pin is set as output mode, the register can be read/written and controls the state of the gpio pin. 8.11.8 simple i/o set 1, 2, 3, 4, 5, and 6 input/output selection registers (index=c8h, c9h, cah, cbh, cch, and cdh, default=00h) bit description 7-0 smio_dir7-0 (simple i/o direction select) these bits determine the directions of the simple i/o pins. 0: input (default). 1: output.
www.ite.com.tw IT8780F v0.3 59 configuration 8.11.9 irq3-7, 9-12 and 14-15 external routing input pin mapping registers (index=e3h-e7h, e9h- ech and eeh-efh, default=00h) these registers are used to determine the external routing input pin mappings of irq3-7, 9-12, and 14-15. bit description 7 reserved 6 en_irq_shr (external interrupt request sharing) 0: normal (default). 1: enable irq sharing. 5-0 irqin_loc (irq input location) please see gpio pins location mapping table note4 on page 64. the related simio_dir (simple i/o direction select) should be set as input. 8.11.10 programmable chip select configuration registers (index=f0h, default=00h) bit description 7-4 cs2_cfg3-0 (programmable chip select 2 configuration) these bits configure the address decoder of programmable chip select 2. the cs2# will be activated when the lpc i/o cycle addresses match the non-masked corresponding base address bits (determined in the programmable chip select 2 base address msb and lsb registers). bits3-0 masked address(es) 0000: no masked address 0001: address 0 0010: addresses [1:0] 0011: addresses [2:0] 1100: addresses [11:0] else: reserved 3-0 cs1_cfg3-0 (programmable chip select 1 configuration) these bits configure the address decoder of programmable chip select 1. the cs1# will be activated when the lpc i/o cycle addresses match the non-masked corresponding base address bits (determined in the programmable chip select 1 base address msb and lsb registers). bits3-0 masked address(es) 0000: no masked address 0001: address 0 0010: addresses [1:0] 0011: addresses [2:0] 1100: addresses [11:0] else: reserved 8.11.11 user-defined memory base address high byte register (index=f1h, default=00h) bit description 7-0 udma31-24 (user-defined memory addresses) 8.11.12 user-defined memory base address low byte register (index=f2h, default=00h) bit description 7-0 udma23-16 (user-defined memory addresses)
www.ite.com.tw IT8780F v0.3 60 IT8780F 8.11.13 user-defined memory size high byte register (index=f3h, default=00h) bit description 7 reserved 6 ctl_mod (control signal mode) this bit selects the mode of the control signals xrd#_xen and xwr#_xdir. if xdir is selected, a high level indicates a read cycle; a low level indicates a write cycle. 0: xrd#/xwr# mode (default). 1: xen/xdir mode. 5 add_mod (address mode) this bit selects the address mode of the xa[23:0]. if the direct mode is selected, xa[23:0] will transfer the lpc addresses directly. if the indirect mode is selected, xa[23:0] will perform 000_0000h for lpc addresses equal to the user-defined memory base address 000_0001h for lpc addresses equal to the user-defined memory base address +1, and so on. 0: direct mode (default). 1: indirect mode. 4 udmen (user-defined memory enable) this bit enables the user-defined memory segment. 0: disable (default). 1: enable. 3-0 udm_siz11-8 (user-defined memory size configuration) these bits configure the size after the user-defined memory base addresses (addresses 31-16 are determined in the user-defined memory base high and low byte registers; addresses 15-0 are 0000h.) of the user-defined memory (udmcs#). please see the user-defined memory size low byte register for details. 8.11.14 user-defined memory size low byte register (index=f4h, default=00h) bit description 7-0 udm_siz7-0 (user-defined memory size configuration) these bits configure the size after the user-defined memory base addresses (addresses 31-16 are determined in the user-defined memory base high and low byte registers; addresses 15-0 are 0000h.) of the user-defined memory (udms#). udm_siz11-0 udms# activates in 000h: base address ~ base address + ffffh 001h: base address ~ base address + 1_ffffh 002h: base address ~ base address + 2_ffffh 003h: base address ~ base address + 3_ffffh ffeh: base address ~ base address + ffe_ffffh fffh: base address ~ base address + fff_ffffh
www.ite.com.tw IT8780F v0.3 61 configuration 8.12 rtc configuration registers (ldn=08h) 8.12.1 rtc activate (index=30h, default=00h or 01h) bit description 7-1 reserved 0 rtc_en (rtc activation) when this bit is set, the rtc function is enabled. the default value depends on the state of the rts1# when lreset# is activated. the default value is 1b for the high state of rts1# when lreset# is activated. it is 0b for the low state of rts1# when lreset# is activated. 0: disabled. 1: rtc enabled. 8.12.2 rtc primary base address msb register (index=60h, default=00h) bit description 7-4 read only with ?0h? for base addresses [15:12]. 3-0 read/write , mapped as base addresses [11:8]. 8.12.3 rtc primary base address lsb register (index=61h, default=70h) bit description 7-1 read/write , mapped as base addresses [7:1]. 0 read only as ?0b.? 8.12.4 rtc secondary base address msb register (index=62h, default=00h) bit description 7-4 read only with ?0h? for base addresses [15:12]. 3-0 read/write , mapped as base addresses [11:8]. 8.12.5 rtc secondary base address lsb register (index=63h, default=72h) bit description 7-1 read/write , mapped as base addresses [7:1]. 0 read only as ?0b.? 8.12.6 rtc interrupt level select (index=70h, default=08h) bit description 7-4 reserved with default ?0h.? 3-0 select the interrupt level note1 for rtc.
www.ite.com.tw IT8780F v0.3 62 IT8780F 8.12.7 rtc interrupt type (index=71h, default=02h) this register indicates the type of interrupt set for rtc and is read only as ?02h? when bit 0 of the rtc special configuration register is cleared. when bit 6 is set, this type of interrupt can be selected as level or edge trigger. bit description 7-2 reserved 1 act_level (active level) 0: low level. 1: high level (default). 0 act_type (active type) 0: edge type. 1: level type. 8.12.8 rtc special configuration register (index=f0h, default=00h) bit description 7 rtc_irq_shr (rtc interrupt request sharing) 0: normal (default). 1: enable rtc irq sharing. 6 irq_type_wr (interrupt type register write enable) 0: type of interrupt of rtc is fixed (default). 1: type of interrupt of rtc can be changed. 5 reserved 4 u128b3_lock (lock bytes 60h~7fh in the upper 128 byte bank ram) this bit is used to lock bytes 60h~7fh in the upper 128 byte bank (bank 1) of ram. this register can only be written once and can only be reset by hardware reset. 0: no lock (default). 1: locks reads and writes to the locations 60h~7fh in the upper 128 byte bank of ram. write cycles will have no effect. read cycles will not return any particular value guaranteed. 3 u128b2_lock (lock bytes 40h~5fh in the upper 128 byte bank ram) this bit is used to lock bytes 40h~5fh in the upper 128 byte bank (bank 1) of ram. this register can only be written once and can only be reset by hardware reset. 0: no lock (default). 1: locks reads and writes to the locations 40h~5fh in the upper 128 byte bank of ram. write cycles will have no effect. read cycles will not return any particular value guaranteed. 2 u128b1_lock (lock bytes 20h~3fh in the upper 128 byte bank ram) this bit is used to lock bytes 20h~3fh in the upper 128 byte bank (bank 1) of ram. this register can only be written once and can only be reset by hardware reset. 0: no lock (default). 1: locks reads and writes to the locations 20h~3fh in the upper 128 byte bank of ram. write cycles will have no effect. read cycles will not return any particular value guaranteed. 1 u128b0_lock (lock bytes 00h~1fh in the upper 128 byte bank ram) this bit is used to lock bytes 00h~1fh in the upper 128 byte bank (bank 1) of ram. this register can only be written once and can only be reset by hardware reset. 0: no lock (default). 1: locks reads and writes to the locations 00h~1fh in the upper 128 byte bank of ram. write cycles will have no effect. read cycles will not return any particular value guaranteed.
www.ite.com.tw IT8780F v0.3 63 configuration rtc special configuration register[cont?d] bit description 0 l128_lock (lock lower 128 byte bank ram) this bit is used to lock bytes 38h~3fh in the lower 128 byte bank (bank 0) of ram. this register can only be written once and can only be reset by hardware reset. 0: no lock (default). 1: locks reads and writes to the locations 38h~3fh in the lower 128 byte bank of ram. write cycles will have no effect. read cycles will not return any particular value guaranteed. note 1 : interrupt level mapping fh-dh: not valid ch: irq12 . . 3h: irq3 2h: not valid 1h: irq1 0h: no interrupt selected note 2 : dma channel mapping 7h-5h: not valid 4h: no dma channel selected 3h: dma3 2h: dma2 1h: dma1 0h: dma0 note 3 : the gpio pins location mapping table location pin name location pin name location pin name 001 000 gpiow10 (pin 1) 011 000 gpio30 (pin 24) 101 000 gpio50 (pin 124) 001 001 gpiow11 (pin 2) 011 001 gpio31 (pin 25) 101 001 gpio51 (pin 55) 001 010 gpiow12 (pin 3) 011 010 gpio32 (pin 26) 101 010 gpio52 (pin 34) 001 011 gpiow13 (pin 4) 011 011 gpio33 (pin 27) 101 011 gpio53 (pin 45) 001 100 gpiow14 (pin 5) 011 100 gpio34 (pin 28) 101 100 gpio54 (pin 54) 001 101 gpiow15 (pin 6) 011 101 gpio35 (pin 29) 101 101 gpio55 (pin 9) 001 110 gpiow16 (pin 7) 011 110 gpio36 (pin 30) 101 110 gpio56 (pin 10) 001 111 gpiow17 (pin 8) 011 111 gpio37 (pin 31) 101 111 gpio57 (pin 13) 010 000 gpio20 (pin 14) 100 000 gpiow40 (pin 20) else reserved 010 001 gpio21 (pin 15) 100 001 gpiow41 (pin 21) - - 010 010 gpio22 (pin 16) 100 010 gpiow42 (pin 35) - - 010 011 gpio23 (pin 17) 100 011 gpiow43 (pin 49) - - 010 100 gpio24 (pin 18) 100 100 gpiow44 (pin 50) - - 010 101 gpio25 (pin 19) 100 101 gpiow45 (pin 51) - - 010 110 gpio26 (pin 22) 100 110 gpiow46 (pin 52) - - 010 111 gpio27 (pin 23) 100 111 gpiow47 (pin 53) - -
www.ite.com.tw IT8780F v0.3 64
www.ite.com.tw IT8780F v0.3 65 functional description 9. functional description 9.1 lpc interface the IT8780F supports the peripheral site of the lpc i/f as described in the lpc interface specification rev.1.0 (sept. 29, 1997). in addition to the required signals (lad3-0, lframe#, lreset#, lclk, which is the same as pciclk.), the IT8780F also supports ldrq# and serirq. 9.1.1 lpc transactions the IT8780F supports some parts of the cycle types described in the lpc i/f specification. memory read and memory write cycles are used for the flash i/f. i/o read and i/o write cycles are used for the programmed i/o cycles. dma read and dma write cycles are used for dma cycles. all of these cycles are characteristic of the single byte transfer. for lpc host i/o read or write transactions, the super i/o module processes a positive decoding, and the lpc interface can respond to the result of the current transaction by sending out sync values on lad[3:0] signals or leave lad[3:0] tri-state depending on its result. for dma read or write transactions, the lpc interface will make reactions according to the dma requests from the dma devices in the super i/o modules and decide whether to ignore the current transaction or not. the fdc and ecp are 8-bit dma devices. so, if the lpc host initializes a dma transaction with data size of 16/32 bits, the lpc interface will process the first 8-bit data and response with a sync ready (0000b) which will terminate the dma burst. the lpc interface will then re-issue another ldrq# message to assert dreqn after finishing the current dma transaction. 9.1.2 ldrq# encoding the super i/o module provides two dma devices: the fdc and the ecp. the lpc interface provides ldrq# encoding to reflect the dreq[3:0] status. two ldrq# messages or different dma channels may be issued back-to-back to trace dma requests quickly. however, four pci clocks will be inserted between two ldrq# messages of the same dma channel to guarantee that there are at least 10 pci clocks for one dma request to change its status. (the lpc host will decode these ldrq# messages and send those decoded dreqn to the legacy dma controller which runs at 4 mhz or 33/8 mhz). 9.2 serialized irq the IT8780F follows the specification of serialized irq support for pci system, rev. 6.0, september 1, 1995, to support the serialized irq feature and is able to interface most pc chipsets. the IT8780F encodes the parallel interrupts to an serirq which will be decoded by the chipset with built-in interrupt controllers (two 8259 compatible modules). 9.2.1 continuous mode when in the continuous mode, the sirq host initiates the start frame of each serirq sequence after sending out the stop frame by itself. (the next start frame may or may not begin immediately after the turn- around state of current stop frame.) the serirq is always activated and sirq host keeps polling all the irqn and system events, even though no irqn status is changed. the serirq enters the continuous mode following a system reset.
www.ite.com.tw IT8780F v0.3 66 IT8780F 9.2.2 quiet mode in the quiet mode, when one sirq slave detects its input irqn/events have been changed, it may initiate the first clock of start frame. the sirq host can then follow to complete the serirq sequence. in the quiet mode, the serirq has no activity following the stop frame until it is initiated by sirq slave, which implies low activity = low mode power consumption. 9.2.3 waveform samples of serirq sequence r pciclk serirq t srt srt srt srt start frame irq0 frame irq1 frame smi# frame irq3 frame srt irq4 frame s/h h s: slave drive h: host drive r: recovery t: turn-around s/h: slave drive when in quiet mode, host drive when in continuous mode (4/6/8)t figure 9-1. start frame timing s: slave drive h: host drive r: recovery t: turn-around i: idle w: waiting pciclk serirq stop frame (quiet) last frame stop frame (continuous) 2 tclk 0~n t, depends on master 3 tclk 0~n tclk idle state last frame start frame rtws h srt h rth1 srt h i figure 9-2. stop frame timing
www.ite.com.tw IT8780F v0.3 67 functional description 9.2.4 serirq sampling slot slot number irqn / events # of clocks past start IT8780F 1 irq0 2 - 2 irq1 5 y 3 smi# 8 y 4 irq3 11 y 5 irq4 14 y 6 irq5 17 y 7 irq6 20 y 8 irq7 23 y 9 irq8 26 y 10 irq9 29 y 11 irq10 32 y 12 irq11 35 y 13 irq12 38 y 14 irq13 41 - 15 irq14 44 y 16 irq15 47 y 17 iochck# 50 - 18 inta# 53 - 19 intb# 56 - 20 intc# 59 - 21 intd# 62 - 32:22 unassigned 95 / 65 -
www.ite.com.tw IT8780F v0.3 68 IT8780F 9.3 general purpose i/o the IT8780F provides six sets (total 43 pins) of flexible i/o control and special functions for the system designers via a set of multi-functional general purpose i/o pins (gpio). the gpio functions will not be performed unless the related enable bits of the gpio multi-function pin selection registers (index 24h, 25h, 26h, and 27h of the global configuration registers) are set. the gpio functions include the simple i/o function and external interrupt routing function. the simple i/o function includes a set of registers, which correspond to the gpio pins. all control bits are divided into six registers, including the polarity (b0h, b1h, b2h, b3h, b4h, and b5h), the pin internal pull-up enable (b8h, b9h, bah, bbh, bch and bdh), data (c0h, c1h, c2h, c3h, c4h and c5h) and input/output selection (c8h, c9h, cah, cbh, cch and cdh) registers. the external interrupt routing function provides a useful feature for motherboard designers. through this function, the parallel interrupts of other on-board devices can be easily re-routed into the serial irq. only irq3-7, 9-12 and 14-15 can be re-routed. the programming method is to fill the location code (note 3 at the end of section 1) to the selected irqn external routing input pin mapping register. gp i/o pin data-bus wr_ input/output select polarity external irq routing pull-up enable wake-up debounce circuit simple i/o register bit-n 1 0 rd_ d- type figure 9-3. general logic of gpiow function gp i/o pin data-bus wr_ input/output select polarity external irq routing pull-up enable simple i/o register bit-n 1 0 rd_ d- type figure 9-4. general logic of gpio function
www.ite.com.tw IT8780F v0.3 69 functional description 9.3.1 serial bus 1. write data: three continuous bytes are required in writing data to serial bus: the IT8780F serial bus interface address byte, the configuration index register byte and then the data byte. 2. read data: if the configuration index register of the serial bus is known as the desired one, a simply read data cycle can be given (the IT8780F serial bus interface address byte, followed by the data byte read from the configuration registers). otherwise, write the address register to the IT8780F configuration registers first (writing the serial bus interface address byte, followed by the address register byte) and then restart to read data from the IT8780F. the serial bus interface address of the IT8780F is 0100111b (or 1010111b, depending on the power-on strapping of pin 34). 9.3.2 the extended interface the IT8780F provides the extended i/f that supports the flash rom i/f for the bios of the system, user- defined memory extension and programmable chip selects for i/o devices. they are the isa-like interfaces for external 8-bit peripherals. 9.3.2.1 the flash rom i/f and the user-defined memory extension the flash rom i/f and user-defined memory translate the qualified memory transactions of the lpc bus. for the memory transactions, all 32 address lines will be qualified. the flash rom i/f supports several fixed memory segments for the legacy system bios. the user-defined memory extension provides a flexible and programmable memory zone for the system designer. the programmable method is to determine the starting address and the memory size. in user-defined memory extension, two address-mapping modes are used to translate 32 address lines of lpc memory cycle to 28 address lines of the extended i/f, the direct mode and the indirect mode. in the direct mode, the 28 least signification bits of the lpc address are directly routed to a27-0 of the extended i/f. in the indirect mode, the address on the extended i/f represents the difference between the current address and the starting address of the lpc addresses. for example, if the current address on lpc cycle is 5 th after the starting address of the selected zone, the address on the extended will be 0000005h. the address on the extended i/f is constituted by two ways: direct address lines and external latches. the direct address lines are xa11-xa4 and xa3-xa0. with the external latches, the address lines are multiplexed with xd7-xd0. the 3 address strobe signals of xstrb2-xstrb0 are used for a27-a20, a19-a12 and a11- a4 (the same as xa11-xa4). for a11-a4, users can select either one of these two ways. xd[ 7:0 ] a[ 27:20 ] a[ 19:12 ] a[ 11:4 ] d[ 7:0 ] xstrb2 xstrb1 xstrb0 xa27-0 available frcs# /udmcs# xwr# xrd# figure 9-5. flash rom i/f and user-defined memory extension write access cycle
www.ite.com.tw IT8780F v0.3 70 IT8780F xd[ 7:0 ] a[ 27:20 ] a[ 19:12 ] a[ 11:4 ] d[ 7:0 ] xstrb2 xstrb1 xstrb0 xa27-0 available frcs# /udmcs# xwr# xrd# figure 9-6. flash rom i/f and user-defined memory extension read access cycle 9.3.2.2 the programmable chip selects extension the programmable chip selects translate the qualified i/o transactions of the lpc bus. for the programmable chip selects, the qualification can be programmed to mask up to 12 least significant address lines. for the programmable chip selects extension, only the direct address lines xa11-xa0 can be used. except the address latches, the programmable chip selects extension i/f is similar to the flash rom i/f and user-defined memory extension.
www.ite.com.tw IT8780F v0.3 71 functional description 9.4 system wake-up control (swc) and acpi 9.4.1 swc general description the system wake-up control (swc) and acpi functional block detects wake-up events including the external and internal events, and generates system interrupts (smi#, irq) and power management signals (pwureq#, pson#) if the related enable registers are set. there are also two led indicators which can control the led to be on, off or blinking. the external events include the followings: 1. sixteen vsb-powered general purpose input/output wake-up events 2. two modem ring indicator events (ri1# and ri2#) 3. mouse events including movement and button pressing (via mclk and mdat) 4. keyboard events (via kclk and kdat) 5. power and sleep buttons pressing events (pwbtin# and slbtin#) the external events include the followings: 1. rtc alarm event 2. legacy module (fdc, serial port 1, serial port 2, and parallel port) interrupt event 3. keyboard interrupt event 4. mouse interrupt event 5. software power-on and power-off request events if any of the external and internal events is received, the swc will set the related status register in pm1b_stst_high or gpe1_sts_0~gpe1_sts_3. based on these events and the routing information written into its registers, the swc generates the irq (via serirq) and smi# if the related enable registers are set (ge0_2irq~ge03_2irq and ge0_2smi~ ge3_2smi, e0h~e3h and e4h~e7 registers of ldn4). the swc also generates the power management signals -- pwureq# and pson#. pm1b_en_high and gpe1_en_0~gpe1_en_3 are the enable registers for pwureq#. ge0_2pon~ge3_2pon registers (f2h~f6h of ldn4) are the enable registers for pson#. when vcc is on, the power button override event (pressing the power button for more than four seconds) will de-assert the signal pson# directly. when vcc is off, a detection of the power button will also assert the signal pson# directly. there are two control bits, rsu_mod1-0 in the power control register, used to control the behavior of the signals pson# and pwureq# after waking-up from a power fail condition (both vcc and vsb are off). slp_sx# is the sleep state input from the south-bridge. the led control register (led_ctl) is programmed to control the behaviors of led1 an led2. the led2_onvsb and led1_onvsb determine the operations when vsb is on and is vcc off. led2blk1-0 and led1blk1-0 control the behaviors when both vsb and vcc are on. so, each led output can be programmed in different operations between vcc off and on states. the registers f0h~ffh of the swc are powered by vpp which is supplied by vsb when vsb is present, and is supplied by vbat when vsb disappears. the other registers of swc are powered by vsb.
www.ite.com.tw IT8780F v0.3 72 IT8780F 9.4.2 acpi registers the acpi registers supported by IT8780F are divided into three groups: 1. pm1 event group (block b): pm1b_sts_low, pm1b_sts_high, pm1b_en_low, and pm1b_en_high. 2. pm1 control group (block b): pm1b_cnt_low and pm1b_cnt_high. 3. general purpose event 1 group: gpe1_sts_0, gpe1_sts_1, gpe1_sts_2, gpe1_sts_3, gpe1_en_0, gpe1_en_1, gpe1_en_2 and gpe1_en_3. all the status register bits behave according to the ?sticky status bit? definition (the bit is set by the high level of the hardware signal and can only be cleared by software writing a one to it) in acpi specification. IT8780F will generate an activation of pwureq# when both the status and enable bits of an event are set simultaneously. all these registers are powered by vsb. the enabled registers are reset to 00h when vsb is powered-up. table 9-1. acpi registers base address offset r/w mnemonic register name 0h ro pm1b_sts_low pm1 status block b low register 1h r/w1c pm1b_sts_high pm1 status block b high register 2h ro pm1b_en_low pm1 enable block b low register 60h and 61h of ldn4 3h r/w pm1b_en_high pm1 enable block b high register 0h ro pm1b_cnt_low pm1 control block b low register 62h and 63h of ldn4 1h r/w pm1b_cnt_high pm1 control block b high register 0h r/w1c gpe1_sts_0 general purpose 1 status 0 register 1h r/w1c gpe1_sts_1 general purpose 1 status 1 register 2h r/w1c gpe1_sts_2 general purpose 1 status 2 register 3h r/w1c gpe1_sts_3 general purpose 1 status 3 register 4h r/w gpe1_en_0 general purpose 1 enable 0 register 5h r/w gpe1_en_1 general purpose 1 enable 1 register 6h r/w gpe1_en_2 general purpose 1 enable 2 register 64h and 65h of ldn4 7h r/w gpe1_en_3 general purpose 1 enable 3 register 9.4.2.1 pm1 status block b low register (pm1b_sts_low) this register, which contains the lower eight bits of the pm1_sts block b registers, belongs to pm1 event group of the acpi fixed-feature space registers. pm1_sts block b register bits are specified by the acpi but are not implemented in the IT8780F. bits 5, 4, 0 have a ?0? value. bit description 7-6 reserved 5 gbl_sts (global lock status) not implemented. this bit is always ?0?. 4 bm_sts (bus master status) not implemented. this bit is always ?0?. 3-1 reserved 0 tmr_sts (pm timer status) not implemented. this bit is always ?0?.
www.ite.com.tw IT8780F v0.3 73 functional description 9.4.2.2 pm1 status block b high register (pm1b_sts_high) bit description 7 wak_sts (wake-up event status) indicates that an enabled wake-up event has occurred. this bit is set only if the system is in a sleep state (s1-s5). writing ?1? will clear this bit; writing ?0? will be ignored. 0: inactive (default). 1: the system is in a sleep state and at least one enabled wake-up event is active. 6-4 reserved 3 ignored. the data written is ignored. the data read is undefined. 2 rtc_sts (rtc event status) indicates that an enabled rtc alarm (both aie of rtc crb and af of rtc crc are set) has occurred. this bit is set by the rtc alarm becoming active. writing ?1? will clear this bit; writing ?0? will be ignored. 0: inactive (default). 1: an rtc alarm has occurred. 1 slpbtn_sts (sleep button event status) indicates that the sleep button was pressed. this feature is compatible with the acpi model for both a ?single-button? and a ?two-button? system. the pwbtin# signal is internally de-bounced. writing ?1? will clear this bit; writing ?0? will be ignored. 0: inactive (default). 1: the sleep button was pressed. 0 pwrbtn_sts (power button event status) indicates that the power button was pressed. this feature is compatible with the acpi model for a ?two-button? system. the slbtin# signal is internally de-bounced. writing ?1? will clear this bit; writing ?0? will be ignored. 0: inactive (default). 1: the power button was pressed. 9.4.2.3 pm1 enable block b low register (pm1b_en_low) this register, which contains the lower eight bits of the pm1_en block b registers, belongs to pm1 event group of the acpi fixed-feature space registers. pm1_en block b register bits are specified by the acpi, but are not implemented in the IT8780F.bits 5 and 0 have a ?0? value. bit description 7-6 reserved 5 gbl_en (global lock enable) not implemented. this bit is always ?0?. 4-1 reserved 0 tmr_en (pm timer enable) not implemented. this bit is always ?0?.
www.ite.com.tw IT8780F v0.3 74 IT8780F 9.4.2.4 pm1 enable block b high register (pm1b_en_ high) bit description 7-3 reserved 2 rtc_en (rtc event enable) enables the rtc alarm to generate a power management event (sci or wake-up). 0: disable event (default). 1: enable event from rtc alarm. 1 slpbtn_en (sleep button event enable) enables sleep button pressing to generate a power management event (sci or wake-up). 0: disable event (default). 1: enable event from sleep button pressing. 0 pwrbtn_en (power button event enable) enables power button pressing to generate a power management event (sci or wake-up). 0: disable event (default). 1: enable event from power button pressing. 9.4.2.5 pm1 control block b low register (pm1b_ cnt _low) bit description 7-3 reserved 2 gbl_rls (global lock release) not implemented. this bit is always ?0?. 1 gbm_rld (bus master request control) not implemented. this bit is always ?0?. 0 sci_en (sci enable) not implemented. this bit is always ?0?. 9.4.2.6 pm1 control block b high register (pm1b_ cnt _high) bit r/w description 7-6 - reserved 5 wo slp_en (sleep enable) this bit may be set in the same write cycle with a new slp_typ2-0 value. 0: inactive (default). 1: update the current state code from the slp_typ2-0 value. 4-2 r/w slp_typ2-0 (sleep type) bits 2-0 function 000 encoded 3-bit value for sn(n=0~5) (default) xxx encoded 3-bit value (except 000) for the remaining 5 sleep state sn(n=0~5) 1 - ignored. the data written is ignored, and the data read is undefined. 0 - reserved
www.ite.com.tw IT8780F v0.3 75 functional description 9.4.2.7 general purpose 1 status 0 register (gpe1_sts_0) this register, containing bits 0-7 of the gpe1_sts register, belongs to the general purpose event 1 group of the acpi fixed-feature space registers. the status bits behave according to the ?sticky status bit? definition (the bit is set by the high level of the hardware signal and is only cleared by writing ?1? to it through software) in the acpi specification. bit description 7 gpiow17_sts (gpiow17 event status) this bit indicates that an active event has been detected at pin 7 of the gpiow set 1. the event has programmable polarity and de-bounce option (see section 8.11.5 and 8.8.19). the bit is set by an active level at the gpiow17 pin. write ?1? to clear this bit. writing ?0? will be ignored. 0: inactive since last cleared (default). 1: an active event has occurred. 6-0 gpiow16_sts to gpiow10_sts (gpiow16-10 event status) these bits are the same as the above for pins 6-0 of the gpiow set 1. 9.4.2.8 general purpose 1 status 1 register (gpe1_sts_1) this register, containing bits 8-15 of the gpe1_sts register, belongs to the general purpose event 1 group of the acpi fixed-feature space registers. the status bits behave according to the ?sticky status bit? definition (the bit is set by the high level of the hardware signal and is only cleared by writing ?1? to it through software) in the acpi specification. bit description 7 gpiow47_sts (gpiow47 event status) this bit indicates that an active event has been detected at pin 7 of the gpiow set 4. the event has programmable polarity and de-bounce option (see section 8.11.5 and 8.8.19). the bit is set by an active level at the gpiow47 pin. write ?1? to clear this bit. writing ?0? will be ignored. 0: inactive since last cleared (default). 1: an active event has occurred. 6-0 gpiow46_sts to gpiow40_sts (gpiow46-40 event status) these bits are the same as the above for pins 6-0 of the gpiow set 4. 9.4.2.9 general purpose 1 status 2 register (gpe1_sts_2) this register, containing bits 16-23 of the gpe1_sts register, belongs to the general purpose event 1 group of the acpi fixed-feature space registers. the status bits behave according to the ?sticky status bit? definition (the bit is set by the high level of the hardware signal and is only cleared by writing ?1? to it through software) in the acpi specification. bit description 7 pbt_evt_sts (power button event status) indicates that the power button was pressed. this bit is similar to the pwrbtn_sts bit in the pm1b_high register. the pwbtin# signal is internally de-bounced. writing ?1? will clear this bit; writing ?0? will be ignored. 0: inactive (default). 1: the power button was pressed. 6 sbt_evt_sts (sleep button event status) indicates that the sleep button was pressed. this bit is similar to the slpbtn_sts bit in the pm1b_high register. the slbtin# signal is internally de-bounced. writing ?1? will clear this bit; writing ?0? will be ignored. 0: inactive (default). 1: the sleep button was pressed.
www.ite.com.tw IT8780F v0.3 76 IT8780F general purpose 1 status 2 register (gpe1_sts_2) [cont?d] bit description 5 kbd_evt3_sts (keyboard event 3 status) this bit indicates that ?pm key 3? was pressed and that the event was identified by the keyboard wake-up detector. this bit is set only if the keyboard wake-up detector is in the ?power management keys? mode. writing ?1? will clear this bit; writing ?0? will be ignored. 0: inactive since last cleared (default). 1: the ?pm key 3? key was pressed on the keyboard. 4 kbd_evt2_sts (keyboard event 2 status) this bit indicates that ?pm key 2? was pressed and that the event was identified by the keyboard wake-up detector. this bit is set only if the keyboard wake-up detector is in the ?power management keys? mode. writing ?1? will clear this bit; writing ?0? will be ignored. 0: inactive since last cleared (default). 1: the ?pm key 2? key was pressed on the keyboard. 3 kbd_evt1_sts (keyboard event 1 status) this bit indicates that a keyboard event occurred and was identified by the keyboard wake-up detector. the event type depends on the selected operating mode for the keyboard wake-up detector. pressing any key mode. pressing a sequence of keys in the ?password? mode. pressing the ?pm key 1? in the ?power management keys? mode. writing ?1? will clear this bit; writing ?0? will be ignored. 0: inactive since last cleared (default). 1: a keyboard event occurred. 2 ms_evt_sts (mouse event status) this bit indicates that a mouse event occurred and was identified by the mouse wake-up detector. writing ?1? will clear this bit; writing ?0? will be ignored. 0: inactive since last cleared (default). 1: a mouse event occurred. 1 ri2_evt_sts (ri2# event status) this bit indicates that an activation of the ring indicator signal was received at serial port 2. writing ?1? will clear this bit; writing ?0? will be ignored. 0: inactive since last cleared (default). 1: an activation of the ring indicator signal was received at the serial port 2. 0 ri1_evt_sts (ri1# event status) this bit indicates that an activation of the ring indicator signal was received at serial port 1. writing ?1? will clear this bit; writing ?0? will be ignored. 0: inactive since last cleared (default). 1: an activation of the ring indicator signal was received at the serial port 1.
www.ite.com.tw IT8780F v0.3 77 functional description 9.4.2.10 general purpose 1 status 3 register (gpe1_sts_3) this register, containing bits 24-31 of the gpe1_sts register, belongs to the general purpose event 1 group of the acpi fixed-feature space registers. the status bits behave according to the ?sticky status bit? definition (the bit is set by the high level of the hardware signal and is only cleared by software writing ?1? to it) in the acpi specification. bit description 7 sw_off_sts (software off event status) this bit indicates that the software wrote a ?1? to the sw_off_ctl bit in the swc_ctl register to request a vcc power off sequence. writing ?1? will clear this bit; writing ?0? will be ignored. 0: inactive since last cleared (default). 1: ?1? was written to the sw_off_ctl bit in the swc_ctl register. 6 sw_on_sts (software on event status) this bit indicates that the software wrote a ?1? to the sw_off_ctl bit in the swc_ctl register to request a vcc power on sequence when the vcc power is off. the sw_on_sts bit can be written only through the serial bus. writing ?1? will clear this bit; writing ?0? will be ignored. 0: inactive since last cleared (default). 1: ?1? was written to the sw_on_ctl bit in the swc_ctl register. 5 reserved 4 mod_irq_sts (module irq event status) this bit indicates that an irq was generated by one of the legacy modules (fdc, parallel port, serial port 1 and 2). for legacy modules irq, this bit is set only if the irq is enabled for wake-up (bit 4 of the standard configuration register at index 70h) and the related module is active. writing ?1? will clear this bit; writing ?0? will be ignored. 0: inactive since last cleared (default). 1: an enable irq, from the legacy module. 3 ms_irq_sts (mouse irq event status) this bit indicates that an irq was generated by the mouse interface section of the kbc module. this bit is set only if the irq is enabled for wake-up (bit4 of the mouse logical device configuration register at index 70h) and the kbc module is active. writing ?1? will clear this bit; writing ?0? will be ignored. 0: inactive since last cleared (default). 1: an enabled irq, from the mouse interface section of the active kbc module. 2 kbd_irq_sts (keyboard irq event status) this bit indicates that an irq was generated by the keyboard interface section of the kbc module. this bit is set only if the irq is enabled for wake-up (bit 4 of the mouse logical device configuration register at index 70h) and the kbc module is active. writing ?1? will clear this bit; writing ?0? will be ignored. 0: inactive since last cleared (default). 1: an enabled irq, from the keyboard interface section of the kbc module is active. 1 p12_evt_sts (port p12 event status) this bit indicates that an active signal was generated by the kbc module, at the p12 pin. this bit is set only if the kbc module is active. writing ?1? will clear this bit; writing ?0? will be ignored. 0: inactive since last cleared (default). 1: an active high signal at the p12 pin was generated by the kbc module. 0 rtc_evt_sts (rtc wake-up alarm event status) this bit indicates that an enabled rtc alarm has occurred. this bit is similar to the rtc_sts bit in the pm1b_sts_high register. writing ?1? will clear this bit; writing ?0? will be ignored. 0: inactive since last cleared (default). 1: an rtc wake-up alarm has occurred.
www.ite.com.tw IT8780F v0.3 78 IT8780F 9.4.2.11 general purpose 1 enable 0 register (gpe1_en_0) this register, containing bits 0-7 of the gpe1_en register, belongs to the general purpose event 1 group of the acpi fixed-feature space registers. the status bits behave according to the ?enable bit? definition (the bit is read/write by software) in the acpi specification. bit description 7 gpiow17_en (gpiow17 event enable). this bit enables an active at pin 7 of the gpiow set 1 to generate a power management event (pwureq#). 0: disable event (default). 1: enable event. 6-0 gpiow16_en to gpiow10_en (gpiow16-10 event enable) these bits are the same as above for pins 6-0 of the gpiow set 1. 9.4.2.12 general purpose 1 enable 1 register (gpe1_en_1) this register, containing bits 8-15 of the gpe1_en register, belongs to the general purpose event 1 group of the acpi fixed-feature space registers. the status bits behave according to the ?enable bit? definition (the bit is read/write by software) in the acpi specification. bit description 7 gpiow47_en (gpiow47 event enable) this bit enables an active at pin 7 of the gpiow set 4 to generate a power management event (pwureq#). 0: disable event (default). 1: enable event. 6-0 gpiow46_en to gpiow40_en (gpiow46-40 event enable) these bits are the same as above for pins 6-0 of the gpiow set 4.
www.ite.com.tw IT8780F v0.3 79 functional description 9.4.2.13 general purpose 1 enable 2 register (gpe1_en_2) this register, containing bits 16-23 of the gpe1_en register, belongs to the general purpose event 1 group of the acpi fixed-feature space registers. the status bits behave according to the ?enable bit? definition (the bit is read/write by software) in the acpi specification. bit description 7 pbt_evt_en (power button event enable) this bit enables power button pressing to generate a power management event (pwureq#). this bit is similar to the pwrbtn_en bit in the pm1b_en_high register. it should be enabled only if the system does not support the pm1b_evt register block. 0: disable event (default). 1: enable event from power button pressing. 6 sbt_evt_en (sleep button event enable) this bit enables sleep button pressing to generate a power management event (pwureq#). this bit is similar to the slpbtn_en bit in the pm1b_en_high register. it should be enabled only if the system does not support the pm1b_evt register block. 0: disable event (default). 1: enable event from sleep button pressing. 5 kbd_evt3_en (keyboard event 3 enable) this bit enables the event of pressing ?pm key 3? (on the keyboard) to generate a power management event (pwureq#). 0: disable event (default). 1: enable event from pressing the ?pm key 3? on the keyboard. 4 kbd_evt2_en (keyboard event 2 enable) this bit enables the event of pressing ?pm key 2? (on the keyboard) to generate a power management event (pwureq#). 0: disable event (default). 1: enable event from pressing the ?pm key 2? on the keyboard. 3 kbd_evt1_en (keyboard event 1 enable) this bit enables the event of pressing any key, key sequence, or ?pm key 1? (on the keyboard) to generate a power management event (pwureq#). 0: disable event (default). 1: enable event from pressing the any key, key sequence, or ?pm key 1? on the keyboard. 2 ms_evt_en (mouse event enable) this bit enables a mouse event, identified by the mouse wake- up detector to generate a power management event (pwureq#). 0: disable event (default). 1: enable the mouse event identified by the mouse wake-up detector. 1 ri2_evt_en (ri2# event enable) this bit enables an activation of the ring indicator signal, which was received at serial port 2, to generate a power management event (pwureq#). this bit indicates that an activation of the ring indicator signal was received at serial port 1. 0: disable event (default). 1: enable the ring indicator event received at the serial port 2. 0 ri1_evt_en (ri1# event enable) this bit enables an activation of the ring indicator signal, which was received at serial port 1, to generate a power management event (pwureq#). 0: disable event (default). 1: enable the ring indicator event received at the serial port 1.
www.ite.com.tw IT8780F v0.3 80 IT8780F 9.4.2.14 general purpose 1 enable 3 register (gpe1_en_3) this register, containing bits 24-31 of the gpe1_en register, belongs to the general purpose event 1 group of the acpi fixed-feature space registers. the status bits behave according to the ?enable bit? definition (the bit is read/write by software) in the acpi specification. bit description 7 sw_off_en (software off event enable). this bit enables the event of the software writing a ?1? to the sw_off_ctl bit in the swc_ctl register to generate a power management event (pwureq#). 0: disable event (default). 1: enable event if the software writing a ?1? to the sw_off_ctl bit in the swc_ctl register. 6 sw_on_en (software on event enable). this bit enables the event of the software writing a ?1? to the sw_on_ctl bit in the swc_ctl register to generate a power management event (pwureq#). 0: disable event (default). 1: enable event if the software writing a ?1? to the sw_on_ctl bit in the swc_ctl register. 5 reserved 4 mod_irq_en (module irq event enable) this bit enables an active irq from one of the legacy modules to generate a power management event (pwureq#) 0: disable event (default). 1: enable event by an active irq from one of the legacy modules. 3 ms_irq_en (mouse irq event enable) this bit enables an active irq generated by the mouse interface section of the kbc module to generate a power management event (pwureq#). 0: disable event (default). 1: enable event from an irq generated by the mouse interface section of the kbc module. 2 kbd_irq_en (keyboard irq event enable) this bit enables an active irq generated by the keyboard interface section of the kbc module to generate a power management event (pwureq#). 0: disable event (default). 1: enable event from an irq generated by the keyboard interface section of the kbc module. 1 p12_evt_en (port p12 event enable) this bit enables an event by an active high signal generated at the p12 pin to generate a power management event (pwureq#). 0: disable event (default). 1: enable event from an active high signal generated at the p12 pin. 0 rtc_evt_en (rtc alarm event enable) this bit enables an rtc alarm to generate a power management event (pwureq#). this bit is similar to the rtc_en bit in the pm1b_en_high register. it should be enabled only if the system does not support the pm1b_evt register block. 0: disable event (default). 1: enable event from rtc alarm.
www.ite.com.tw IT8780F v0.3 81 functional description 9.5 real time clock (rtc) 9.5.1 general description the rtc device incorporates a timer module that includes a time of day clock and a multi-century calendar, alarm facilities, and three programmable timer interrupts, 242-bytes ram contents which can be backup by the external battery during the power loss, and the power management circuitry which can reduce the standby current when the power is supplied by the vbat. the rtc?s alarm and calendar registers support both bcd and binary modes, and both 24- and 12-hour formats. there is only an interrupt line requested to handle three interrupt conditions, the alarm interrupt, the periodic interrupt, and the update-ended interrupt. the rtc also incorporates a power switching circuitry which can detect the absence of vsb power and switch the power core of the whole block (including ram block) to vbat, and a power-saving circuitry which can reduce the power consumption when the power is switched to vbat. the ram contents are divided into two parts: lower bank (114 bytes) and upper bank (128 bytes). access to the ram may be selectively locked. see section 8.12.8 ?rtc special configuration register? for details. 9.5.2 registers 9.5.2.1 partition the rtc device has three battery-backed register banks which can be accessed by two sets of address ports. battery-backup power enables all these information retention during system power down. ? bank 0 : the first 14 bytes of this bank store time and alarm data and contain control registers. the next 114 bytes are general purpose ram. this bank (00h~7fh) can be accessed through the addresses rtc primary base address (index) and rtc primary base address +1 (data). the rtc primary base address with default 70h can be reassigned in chip configuration registers. ? bank 1 : the total 128 bytes of this bank are another block of general purpose ram. this bank (00h~7fh) can be accessed through the addresses rtc second base address (index) and rtc second base address +1 (data). the rtc second base address with default 72h can also be reassigned in chip configuration registers. ? bank 2 : the total 9 bytes of this bank include century reading and the second alarm registers. this bank (c0h~c8h) can be accessed through the addresses rtc second base address (index) and rtc second base address +1 (data). it shares with the bank 1. 9.5.2.2 register description refer to table 9-2, the register address map of rtc bank 0, to see 10 time registers and 4 control registers. to initialize the time, calendar and alarm a registers properly, the set bit of crb must be set to ?1? to avoid the generation of the update cycle. after the time, calendar, and alarm registers are written, the set bit must be set to 0 to enable the update cycle. when the time corresponds to the alarm time, the alarm will occur once per day. if the data in the hours-alarm register is between c0 to ff, the alarm will generate once per hour if the data in the minutes and seconds register corresponds to the data in the minutes-alarm and seconds-alarm registers. if both the data of hours-alarm and minutes-alarm registers are located between c0 to ff, the alarm will occur once per minute if the data in the seconds register corresponds to the one in the seconds-alarm register. if all data of the hours-alarm, minutes-alarm and seconds-alarm registers are located between c0 to ff, the alarm will generate once per second.
www.ite.com.tw IT8780F v0.3 82 IT8780F table 9-2. rtc register list, bank 0 (primary address, default = 70h/71h) range index function decimal range binary data mode bcd data mode 0 seconds 0-59 00-3b 00-59 1 seconds alarm 0-59 00-3b 00-59 2 minutes 0-59 00-3b 00-59 3 minutes alarm 0-59 00-3b 00-59 hours 12-hr mode 1-12 01-0c am 81-8c pm 01-12 am 81-92 pm 4 hours 24-hr mode 0-23 00-17 00-23 hours alarm 12-hr 1-12 01-0c am 81-8c pm 01-12 am 81-92 pm 5 hours alarm 24-hr 0-23 00-17 00-23 6 day of the week (sunday=1) 1-7 01-07 01-07 7 date of the month 1-31 01-1f 01-31 8 month 1-12 01-0c 01-12 9 year 0-99 00-63 00-99 a control register a (cra) r/w * bit 7 is read only b control register b (crb) r/w * bit 0 is read only c control register c (crc) read only d control register d (crd) read only e-7f general purpose r/w 114 byte table 9-3. rtc register list, bank 1 (second address, default = 72h/73h) index function description 0-7f general purpose r/w 128 bytes table 9-4. rtc register list, bank 2 (second address, default = 72h/73h) range index function decimal range binary data mode bcd data mode c0h century 0-99 00-63 00-99 c1h seconds wake-up 0-59 00-3b 00-59 c2h minutes wake-up 0-59 00-3b 00-59 hours wake-up (12-hr mode) 1-12 01-0c am 81-8c pm 01-12 am 81-92 pm c3h hours wake-up (24-hr mode) 0-23 00-17 00-23 c4h day of the week wake-up 1-7 01-07 01-07 c5h date of the month wake-up 1-31 01-1f 01-31 c6h month wake-up 1-12 01-0c 01-12 c7h year wake-up 0-99 00-63 00-99 c8h century wake-up 0-99 00-63 00-99 c9h rtc wake-up status -- -- --
www.ite.com.tw IT8780F v0.3 83 functional description 9.5.2.2.1 rtc control register a (cra), bank 0 bit r/w description 7 r/w uip (update in progress) uip can be cleared by set=1, but cannot be modified by lreset#. 1: update cycle is in progress or will occur soon. 0: update cycle is not in progress and will not occur for at least 244 s. 6-4 r/w dv2-0 (divider chain control) select the conditions of divider chain, and these three bits are not affected by reset. dv2-0 mode 000b oscillator disabled 001b oscillator disabled 010b normal operation, oscillator on and divider chain enabled 10xb test 11xb oscillator on and divider chain disabled 3-0 r/w rs3-0 (periodic interrupt rates select) select one of fifteen states on the divider or disable the divider output, and these four bits are not affected by lreset#. rs3-0 periodic rate of interrupt 0000b none 0001b 3.90625 ms 0010b 7.8125 ms 0011b 122.070 s 0100b 244.141 s 0101b 488.281 s 0110b 976.562 s 0111b 1.953125 ms 1000b 3.90635 ms 1001b 7.8125 ms 1010b 15.625 ms 1011b 31.25 ms 1100b 62.5 ms 1101b 125 ms 1110b 250 ms 1111b 500 ms
www.ite.com.tw IT8780F v0.3 84 IT8780F 9.5.2.2.2 rtc control register b (crb), bank 0 bit r/w description 7 r/w set set cannot be modified by master reset or any internal functions. 0: execute update cycle once per second. 1: update cycle is disabled and the initial time and calendar bytes can be written. 6 r/w pie (periodic interrupt enable) pie can be cleared by master reset and cannot be modified by any internal functions. the generation rate of the periodic interrupt is determined by ds3-0 in cra. 0: disable the generation of the periodic interrupt. 1: enable the generation of the periodic interrupt. 5 r/w aie (alarm interrupt enable) aie can be cleared by master reset and cannot be modified by any internal functions. the alarm interrupt is generated immediately after a time update which the seconds, minutes, hours, and day-of-month time is equal to their respective alarm counterparts. 0: disable the generation of the alarm interrupt. 1: enable the generation of the alarm interrupt. 4 r/w uie (update-ended interrupt enable) this bit will be cleared by master reset. this interrupt is generated at the time when an update occurs. 0: disable the generation of the update-ended interrupt. 1: enable the generation of the update-ended interrupt. 3 r/w unused the original definition of 146818 is ?square wave enable?, but is not supported by the rtc of this chip. writing to this bit has no effects. 2 r/w dm (data mode) this bit selects the data mode and is not affected by master reset. 0: data in the time and calendar registers are in bcd format. 1: data in the time and calendar registers are in binary format. 1 r/w 24/12 (24- or 12-hour) this bit selects the hour format, and it is not affected by master reset. 0: 12-hour format. 1: 24-hour format. 0 r/w dse (daylight saving enable) this bit selects the hour format, and it is not affected by master reset. in spring, time advances from 1:59:59 to 3:00:00 on the first sunday in april. in fall, time returns from 1:59:59 to 1:00:00 on the last sunday in october. 0: disable daylight saving mode. 1: enable daylight saving mode.
www.ite.com.tw IT8780F v0.3 85 functional description 9.5.2.2.3 rtc control register c (crc), bank 0 the rtc supports three interrupt events: periodic interrupt, alarm interrupt, and update-ended interrupt. when an interrupt occurs, the related flag bit is set to ?1? in crc. these flag bits are set despite the status of the corresponding enable bits in crb. only when the interrupt enable bit is set and the corresponding interrupt flag bit is set, the irqf bit in crc will be activated and irq of rtc is pulled low. the state of the interrupt flag bits and rtc irq will not be cleared until the read cycle of crc is completed. bit r/w description 7 ro irqf (interrupt request flag) this bit is inverse of the value on the irq output signal of the rtc module. 0: rtc irq is inactive. 1: rtc irq is active when both pf and pie are 1; or both af and aie are 1; or both uf and uie are 1. 6 ro pf (periodic interrupt flag) pf can be cleared by master reset and reading this register. 0: no transition occurred on the selected tap since last read. 1: at least a transition occurred on the selected tap since last read. 5 ro af (alarm interrupt flag) af can be cleared by master reset and reading this register. 0: no alarm was detected since last read. 1: an alarm condition was detected. 4 ro uf (update-ended interrupt flag) this bit will be cleared by master reset and reading this register. 0: disable the generation of the update-ended interrupt. 1: enable the generation of the update-ended interrupt. 3-0 - reserved 9.5.2.2.4 rtc control register d (crd), bank 0 bit r/w description 7 ro vrt (valid ram and time) this bit is affected by master reset, and can only be set if the vbat voltage is not too low when crd is read. 0: the voltage of vbat is too low. 1: the contents of rtc and ram are valid. 6 - reserved 5-0 r/w date_alarm (date alarm bits) these six bits, which are not affected by master reset, store the date of month alarm value. if set to 000000b, the date alarm is ?don?t care?. the legal values for these six bits are 01 to 31 in bcd format and 01 to 1f in binary format.
www.ite.com.tw IT8780F v0.3 86 IT8780F 9.5.2.2.5 the function of wake-up alarm, bank 2 wake-up alarm registers are used to set the wake up alarm time. when the wake up alarm time specified is up while the hardware will set rtc_evt_sts of gpe1_sts_2. if the related enabled bits are set, the wake- up alarm event may cause activation of pson#, pwureq#, siosmi#, and swc irq. when all of the eight wake-up alarm registers (with addresses from c1h to c8h) are set in an appropriate time, the alarm signal will occur at the specified time. the wake-up alarm registers can also serve to set bits[7:6] of one or more wake-up alarm registers to ?11? to create a ?don?t care? situation. take the hours wake-up alarm register for example. the alarm will be generated once per hour if the first two bits of hour wake-up alarm register are set to ?11.? an ?or? function is provided for day of week wake-up alarm (c4h) and date of month wake-up alarm (c5h) registers. the alarm will be generated once every day if bits[7:6] of the above two registers are set to ?11,? which will result in ?don?t care? situation. the alarm is generated on the day of month when the date of month wake-up alarm (c5h) is written with appropriate data and the day of week wake-up alarm (c4h) is ?don?t care.? (bits[7:6] are set to ?11.?) the alarm is generated on the day of week if the date of month wake- up alarm (c5h) is ?don?t care,? (bits[7:6] are set to ?11.?), and the day of week wake-up alarm (c4h) is written with appropriate data. when both of the two registers are written with appropriate data except ?don?t care,? the alarm will be generated on either the day of week or the day of month. 9.6 floppy disk controller (fdc) 9.6.1 introduction the floppy disk controller provides the interface between a host processor and up to two floppy disk drives. it integrates a controller and a digital data separator with write precompensation, data rate selection logic, microprocessor interface, and a set of registers. the fdc supports data transfer rates of 250 kbps, 300 kbps, 500 kbps, and 1 mbps. it operates in pc/at mode and supports 3-mode type drives. additionally, the fdc is software compatible with the 82077. the fdc configuration is handled by software and a set of configuration registers. status, data, and control registers facilitate the interface between the host microprocessor and the disk drive, providing information about the condition and/or state of the fdc. these configuration registers can select the data rate, enable interrupts, drives and dma modes, and indicate errors in the data or operation of the fdc/fdd. the controller manages data transfers using a set of data transfer and control commands. these commands are handled in three phases: command, execution and result. not all commands utilize all these three phases. 9.6.2 reset the IT8780F device implements both software and hardware reset options for the fdc. either type of the resets will reset the fdc, terminating all operations and placing the fdc into an idle state. a reset during a write to the disk will corrupt the data and the corresponding crc. 9.6.3 hardware reset (lreset# pin) when the fdc receives a lreset# signal, all registers of the fdc core are cleared (except those programmed by the specify command). to exit the reset state, the host must clear the dor bit.
www.ite.com.tw IT8780F v0.3 87 functional description 9.6.4 software reset (dor reset and dsr reset) when the reset bit in the dor or the dsr is set, all registers of the fdc core are cleared. a reset performed by setting the reset bit in the dor has higher priority over a reset performed by setting the reset bit in the dsr. in addition, to exit the reset state, the dsr bit is self-clearing, while the host must clear the dor bit. 9.6.5 digital data separator the internal digital data separator is comprised of a digital pll and associated support circuitry. it is responsible for synchronizing the raw data signal read from the floppy disk drive. the synchronized signal is used to separate the encoded clock from the data pulses. 9.6.6 write precompensation write precompensation is a method that can be used to adjust the effects of bit shift on data as it is written to the disk. it is harder for the data separator to read data that has been subject to bit shifting. soft read errors can occur due to such bit shifting. write precompensation predicts where the bit shifting might occur within a data pattern and shifts the individual data bits back to their nominal positions. the fdc permits the selection of writes precompensation via the data rate select register (dsr) bits 2 through 4. 9.6.7 data rate selection selecting one of the four possible data rates for the attached floppy disks is accomplished by setting the diskette control register (dcr) or data rate select register (dsr) bits to 0 and 1. the data rate is determined by the last value that is written to either the dcr or the dsr. when the data rate is set, the data separator clock is scaled appropriately. 9.6.8 status, data and control registers 9.6.8.1 digital output register (dor, fdc base address + 02h) this is a read/write register. it controls drive selection and motor enables as well as a software reset bit and dma enable. the i/o interface reset may be used at any time to clear the dor?s contents. table 9-5. digital output register (dor) bit r/w description 7-6 r/w reserved 5 r/w motben (drive b motor enable) 0: disable drive b motor. 1: enable drive b motor. 4 r/w motaen (drive a motor enable) 0: disable drive a motor. 1: enable drive a motor. 3 r/w dmaen (disk interrupt and dma enable) 0: disable disk interrupt and dma (drqx, dackx#, tc and intx). 1: enable disk interrupt and dma. 2 r/w reset# (fdc function reset) 0: reset fdc function. 1: clear reset of fdc function. this reset does not affect the dsr, dcr or dor. 1 - reserved 0 r/w dvsel (drive selection) 0: select drive a. 1: select drive b.
www.ite.com.tw IT8780F v0.3 88 IT8780F 9.6.8.2 tape drive register (tdr, fdc base address + 03h) this is a read/write register and is included for 82077 software compatibility. the contents of this register are not used internal to the device. table 9-6. tape drive register (tdr) bit r/w description 7-2 - undefined 1-0 r/w tp_sel[1:0] (tape drive selection) tp_sel[1:0] : drive selected. 00: none 01: 1 10: 2 11: 3 9.6.8.3 main status register (msr, fdc base address + 04h) this is a read only register. it indicates the general status of the fdc, and is able to receive data from the host. the msr should be read before each byte is sent to or received from the data register, except when in dma mode. table 9-7. main status register (msr) bit r/w description 7 ro rqm (fdc request for master) 0: the fdc is busy and cannot receive data from the host. 1: the fdc is ready and the host can transfer data. 6 ro dio (data i/o direction) indicates the direction of data transfer once a rqm has been set. 0: write. 1: read. 5 ro ndm (non-dma mode) this bit selects non-dma mode of operation. 0: dma mode selected. 1: non-dma mode selected. this mode is selected via the specify command during the execution phase of a command. 4 ro cb (diskette control busy) indicates whether a command is in progress (the fdd is busy) or not. 0: a command has been executed and the end of the result phase has been reached. 1: a command is being executed. 3-2 - reserved 1 ro dbb (drive b busy) indicates whether drive b is in the seek portion of a command. 0: not busy. 1: busy. 0 dab (drive a busy) indicates whether drive a is in the seek portion of a command. 0: not busy. 1: busy.
www.ite.com.tw IT8780F v0.3 89 functional description 9.6.8.4 data rate select register (dsr, fdc base address + 04h) this is a write only register. it is used to determine the data rate, amount of write precompensation, power down mode, and software reset. the data rate of the floppy disk controller is the latest write of either the dsr or dcr. the dsr is unaffected by a software reset. the dsr can be set to 02h by a hardware reset. the ?02h? represents the default precompensation, and 250 kbps indicates the data transfer rate. table 9-8. data rate select register (dsr) bit r/w description 7 wo s/w reset (software reset) it is active high and shares the same function with the reset# of the dor except that this bit is self-clearing. 6 wo powe down (power down) when this bit is written with a ?1?, the floppy controller is put into manual low power mode. the clocks of the floppy controller and data separator circuits will be turned off until a software reset or the data register or main status register is accessed. 5 - undefined 4-2 wo pre-comp 2-0 (precompensation select) these three bits are used to determine the value of write precompensation that will be applied to the wdata# pin. track 0 is the default starting track number, which can be changed by the configure command for precompensation. pre_comp precompensation delay 111 001 010 011 100 101 110 000 0.0 ns 41.7 ns 83.3 ns 125.0 ns 166.7 ns 208.3 ns 250.0 ns default default precompensation delays data rate precompensation delay 1 mbps 500 kbps 300 kbps 250 kbps 41.7 ns 125.0 ns 125.0 ns 125.0 ns drate1-0 (data rate select) 1-0 wo bits 1-0 00 01 10 11 data transfer rate 500 kbps 300 kbps 250 kbps (default) 1 mbps
www.ite.com.tw IT8780F v0.3 90 IT8780F 9.6.8.5 data register (fifo, fdc base address + 05h) this is an 8-bit read/write register. it transfers command information, diskette drive status information, and the result phase status between the host and fdc. the fifo consists of several registers in a stack. only one register in the stack is permitted to transfer information or status to the data bus at a time. table 9-9. data register (fifo) bit r/w description 7-0 r/w data command information, diskette drive status, or result phase status data. 9.6.8.6 digital input register (dir, fdc base address + 07h) this is a read only register and shares this address with the diskette control register (dcr). table 9-10. digital input register (dir) bit r/w description 7 r/w dskchg (diskette change) indicates the inverting value of the bit monitored from the input of the floppy disk change pin (dskchg#). 6-0 - undefined. 9.6.8.7 diskette control register (dcr, fdc base address + 07h) this register is write only and shares this address with the digital input register (dir). the dcr register controls the data transfer rate for the fdc. table 9-11. diskette control register (dcr) bit r/w description 7-2 - reserved . always 0. drate (data rate select) 1-0 wo bits 1-0 00 01 10 11 data transfer rate 500 kbps 300 kbps 250 kbps 1 mbps 9.6.9 controller phases the fdc handles data transfers and control commands in three phases: command, execution and result. not all commands utilize these three phases.
www.ite.com.tw IT8780F v0.3 91 functional description 9.6.9.1 command phase upon reset, the fdc enters the command phase and is ready to receive commands from the host. the host must verify that msr bit 7 (rqm) = 1 and msr bit 6 (dio) = 0, indicating the fdc is ready to receive data. for each command, a defined set of command code and parameter bytes must be transferred to the fdc in a given order. see section 9.6.11 and 9.6.12 for details on the various commands. rqm is set false (0) after each byte-read cycle, and set true (1) when a new parameter byte is required. the command phase is completed when this set of bytes has been received by the fdc. the fdc automatically enters the next controller phase and the fifo is disabled. 9.6.9.2 execution phase upon the completion of the command phase, the fdc enters the execution phase. it is in this phase that all data transfers occur between the host and fdc. the specify command indicates whether this data transfer occurs in dma or non-dma mode. each data byte is transferred via an irqx or drqx# based upon the dma mode. on reset, the configure command can automatically enable or disable the fifo. the execution phase is completed when all data bytes have been received. if the command executed does not require a result phase, the fdc is ready to receive the next command. 9.6.9.3 result phase for commands that require data written to the fifo, the fdc enters the result phase when the irq or drq is activated. the msr bit 7 (rqm) and msr bit 6 (dio) must equal to 1 to read the data bytes. the result phase is completed when the host has read each of the defined set of result bytes for the given command. right after the completion of the phase, rqm is set to 1, dio is set to 0, and the msr bit 4 (cb) is cleared, indicating the fdc is ready to receive the next command. 9.6.9.4 result phase status registers for commands that contain a result phase, these read only registers indicate the status of the latest executed command. table 9-12. status register 0 (st0) bit r/w description 7-6 ro ic (interrupt code) 00: execution of the command has been completed correctly. 01: execution of the command began, but failed to complete successfully. 10: invalid command. 11: execution of the command was not completed correctly due to a polling error. 5 ro se (seek end) the fdc executed a seek or re-calibrate command. 4 ro ec (equipment check) the trk0# pin was not set after a re-calibrate command was issued. 3 ro nu (not used) 2 ro h (head address) the current head address. 1 ro dsb (drive b select) drive b selected. 0 ro dsa (drive a select) drive a selected.
www.ite.com.tw IT8780F v0.3 92 IT8780F table 9-13. status register 1 (st1) bit r/w description 7 ro en (end of cylinder) indicates the fdc attempted to access a sector beyond the final sector of the track. this bit will be set if the terminal count (tc) signal is not issued after a read data or write data command. 6 ro nu (not used) 5 ro de (data error) a crc error occurred in either the id field or the data field of a sector. 4 ro or (overrun/ underrun) an overrun on a read operation or underrun on a write operation occurs when the fdc is not serviced by the cpu or dma within the required time interval. 3 ro nu (not used) 2 ro nd (no data) no data are available to the fdc when either of the following conditions is met: the floppy disk cannot find the indicated sector while the read data or read deleted data commands are executed. while executing a read id command, an error occurs upon reading the id field. while executing a read a track command, the fdc cannot find the starting sector. 1 ro nw (not writeable) set when a write data, write deleted data, or format a track command is being executed on a write-protected diskette. 0 ro ma (missing address mark) this flag bit is set when either of the following conditions is met: the fdc cannot find a data address mark or a deleted data address mark on the specified track the fdc cannot find any id addresses on the specified track after two index pulses are detected from the index# pin. table 9-14. status register 2 (st2) bit r/w description 7 ro nu (not used) 6 ro cm (control mark) this flag bit is set when either of the following conditions is met: the fdc finds a deleted data address mark during a read data command. the fdc finds a data address mark during a read deleted data command. 5 ro dd (data error in data field) this flag bit is set when a crc error is found in the data field. 4 ro wc (wrong cylinder) this flag bit is set when the track address in the id field is different from the track address specified in the fdc. 3 ro sh (scan equal hit) this flag bit is set when the condition of "equal" is satisfied during a scan command. 2 ro sn (scan not satisfied) this flag bit is set when the fdc cannot find a sector on the cylinder during a scan command. 1 ro bc (bad cylinder) this flag bit is set when the track address equals to ?ffh? and is different from the track address in the fdc. 0 ro md (missing data address mark) this flag bit is set when the fdc cannot find a data address mark or deleted data address mark.
www.ite.com.tw IT8780F v0.3 93 functional description table 9-15. status register 3 (st3) bit r/w description 7 ro ft (fault) indicates the current status of the fault signal from the fdd. 6 ro wp (write protect) indicates the current status of the write protect signal from the fdd. 5 ro rdy (ready) indicates the current status of the ready signal from the fdd. 4 ro tk0 (track 0) indicates the current status of the track 0 signal from the fdd. 3 ro ts (two side) indicates the current status of the two side signal from the fdd. 2 ro hd (head address) indicates the current status of the head select signal to the fdd. 1-0 ro us1, us0 (unit select) indicates the current status of the unit select signals to the fdd. 9.6.10 command set the fdc utilizes a defined set of commands to communicate with the host. each command is comprised of a unique first byte, which contains the op-code, and a series of additional bytes, which contain the required set of parameters and results. the descriptions use a common set of parameter byte symbols, which are presented in table 9-16. the fdc commands may be executed whenever the fdc is in the command phase. the fdc checks to see that the first byte is a valid command and, if so, proceeds. an interrupt is issued if it is not a valid command.
www.ite.com.tw IT8780F v0.3 94 IT8780F table 9-16. command set symbol descriptions symbol name description c cylinder number the current/selected cylinder (track) number: 0 ? 255. d data the data pattern to be written into a sector. dc3 ? dc0 drive configuration bit3-0 designate which drives are perpendicular drives on the perpendicular mode command. dir direction control read/write head step direction control. 0 = step out; 1 = step in. dr0, dr1 disk drive select the selected drive number: 0 or 1. dtl data length when n is defined as 00h, dtl designates the number of data bytes which users are going to read out or write into the sector. when n is not 00h, dtl is undefined. dfifo disable fifo a ?1? will disable the fifo (default). a ?0? will enable the fifo. ec enable count if ec=1, dtl of verify command will be sc. eis enable implied seek if eis=1, a seek operation will be performed before executing any read or write command that requires the c parameter. eot end of track the final sector number on a cylinder. during a read or write operation, the fdc stops data transfer after the sector number is equal to eot. gap2 gap 2 length by perpendicular mode command, this parameter changes gap 2 length in the format. gpl gap length the length of gap 3. during a format command, it determines the size of gap 3. h head address the head number 0 or 1, as specified in the sector id field. (h = hd in all command words.) hd head the selected head number 0 or 1. it also controls the polarity of hdsel#. (h = hd in all command words.) hlt head load time the head load time in the fdd (2 to 254 ms in 2 ms increments). hut head unload time the head unload time after a read or write operation has been executed (16 to 240 ms in 16 ms increments). lock if lock=1, dfifo, fifothr, and pretrk parameters of the configure command will not be affected by a software reset. if lock=0 (default), the above parameters will be set to their default values following a software reset. mfm fm or mfm mode if mfm is low, fm mode (single density) is selected. if mfm is high, mfm mode (double density) is selected. mt multi-track if mt is high, a multi-track operation is to be performed. in this mode, the fdc will automatically start searching for sector 1 on side 1 after finishing a read/write operation on the last sector on side 0. n number the number of data bytes written into a sector, where: 00 = 128 bytes (pc standard) 01 = 256 bytes 02 = 512 bytes ? 07 = 16 kbytes ncn new cylinder number a new cylinder number, which is to be reached as a result of the seek operation. desired position of head. nd non-dma mode when nd is high, the fdc operates in the non-dma mode.
www.ite.com.tw IT8780F v0.3 95 functional description table 9-16. command set symbol descriptions [cont?d] symbol name description ow overwrite if ow=1, dc3-0 of the perpendicular mode command can be modified. otherwise, those bits cannot be changed. pcn present cylinder number the cylinder number at the completion of a sense interrupt status command. position of head at present time. polld polling disable if polld=1, the internal polling routine is disabled. pretrk precompensatio n starting track number programmable from track 0 ?255. r record the sector number, which will be read or written. rcn relative cylinder number to determine the relative cylinder offset from present cylinder as used by the relative seek command. sc the number of sectors per cylinder. sk skip if sk=1, the read data operation will skip sectors with a deleted data address mark. otherwise, the read deleted data operation only accesses sectors with a deleted data address mark. srt step rate time the stepping rate for the fdd (1 to 16 ms in 1 ms increments). stepping rate applies to all drives (f=1 ms, e=2 ms, etc.). st0 st1 st2 st3 status 0 status 1 status 2 status 3 st0 ? 3 stand for one of four registers that store the status information after a command has been executed. this information is available during the result phase after command execution. these registers should not be confused with the main status register (selected by a 0 = 0). st0 ? 3 may be read only after a command has been executed and contain information associated with that particular command. stp if stp = 1 during a scan operation, the data in contiguous sectors are compared byte by byte with data sent from the processor (or dma). if stp = 2, alternate sectors are read and compared.
www.ite.com.tw IT8780F v0.3 96 IT8780F table 9-17. command set summary read data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks wo mt mfm sk 0 0 1 1 0 command codes wo 0 0 0 0 0 hds dr1 dr0 wo c wo h wo r wo n wo eot wo gpl command wo dtl sector id information before the command execution execution data transfer between the fdd and the main system ro st0 ro st1 ro st2 status information after command execution ro c ro h ro r result ro n sector id information after command execution read deleted data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks wo mt mfm sk 0 1 1 0 0 command codes wo 0 0 0 0 0 hds dr1 dr0 wo c wo h sector id information before the command execution wo r wo n wo eot wo gpl command wo dtl execution data transfer between the fdd and the main system ro st0 ro st1 status information after command execution ro st2 ro c ro h sector id information after command execution ro r result ro n
www.ite.com.tw IT8780F v0.3 97 functional description read a track data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks wo 0 mfm 0 0 0 0 1 0 command codes wo 0 0 0 0 0 hds dr1 dr0 wo c wo h sector id information before the command execution wo r wo n wo eot wo gpl command wo dtl execution data transfer between the fdd and main system cylinder's contents from index hole to eot ro st0 ro st1 status information after the command execution ro st2 ro c ro h sector id information after command execution ro r result ro n write data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks wo mt mfm 0 0 0 1 0 1 command codes wo 0 0 0 0 0 hds dr1 dr0 wo c wo h sector id information before the command execution wo r wo n wo eot wo gpl command wo dtl execution data transfer between the fdd and main system ro st0 ro st1 status information after command execution ro st2 ro c ro h sector id information after command execution ro r result ro n
www.ite.com.tw IT8780F v0.3 98 IT8780F write deleted data data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks wo mt mfm 0 0 1 0 0 1 command codes wo 0 0 0 0 0 hds dr1 dr0 wo c wo h sector id information before the command execution wo r wo n wo eot wo gpl command wo dtl execution data transfer between the fdd and main system ro st0 ro st1 status information after command execution ro st2 ro c ro h sector id information after command execution ro r result ro n format a track data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks wo 0 mfm 0 0 1 1 0 1 command codes wo 0 0 0 0 0 hds dr1 dr0 wo n bytes/sector wo sc sectors/cylinder wo gpl gap 3 command wo d filler byte wo c wo h wo r execution for each sector repeat: wo n input sector parameters per- sector fdc formats an entire cylinder ro st0 ro st1 ro st2 status information after command execution ro undefined ro undefined ro undefined result ro undefined
www.ite.com.tw IT8780F v0.3 99 functional description scan equal data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks wo mt mfm sk 1 0 0 0 1 command codes wo 0 0 0 0 0 hds dr1 dr0 wo c wo h sector id information before the command execution wo r wo n wo eot wo gpl command wo dtl execution data transferred from the system to controller is compared to data read from disk ro st0 ro st1 status information after command execution ro st2 ro c ro h sector id information after command execution ro r result ro n scan low or equal data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks wo mt mfm sk 1 1 0 0 1 command codes wo 0 0 0 0 0 hds dr1 dr0 wo c wo h sector id information before the command execution wo r wo n wo eot wo gpl command wo dtl execution data transferred from the system to controller is compared to data read from disk ro st0 ro st1 status information after command execution ro st2 ro c ro h sector id information after command execution ro r result ro n
www.ite.com.tw IT8780F v0.3 100 IT8780F scan high or equal data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks wo mt mfm sk 1 1 1 0 1 command codes wo 0 0 0 0 0 hds dr1 dr0 wo c wo h sector id information before the command execution wo r wo n wo eot wo gpl command wo dtl execution data transferred from the system to controller is compared to data read from disk ro st0 ro st1 status information after command execution ro st2 ro c ro h sector id information after command execution ro r result ro n verify data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks wo mt mfm sk 1 0 1 1 0 command codes wo ec 0 0 0 0 hds dr1 dr0 wo c wo h sector id information before the command execution wo r wo n wo eot wo gpl command wo dtl/sc execution no data transfer takes place ro st0 ro st1 status information after command execution ro st2 ro c r h sector id information after command execution ro r result ro n
www.ite.com.tw IT8780F v0.3 101 functional description read id data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks wo 0 mfm 0 0 1 0 1 0 command codes command wo 0 0 0 0 0 hds dr1 dr0 execution the first correct id information on the cylinder is stored in the data register ro st0 ro st1 status information after command execution ro st2 ro c ro h sector id information during execution phase ro r result ro n configure data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks wo 0 0 0 1 0 0 1 1 configure information wo 0 0 0 0 0 0 0 0 wo 0 eis dfifo polld fifothr command pretrk execution re-calibrate data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks wo 0 0 0 0 0 1 1 1 command codes command wo 0 0 0 0 0 0 dr1 dr0 execution head retracted to track 0 seek data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks wo 0 0 0 0 1 1 1 1 command codes wo 0 0 0 0 0 hds dr1 dr0 command wo ncn execution head is positioned over proper cylinder on diskette
www.ite.com.tw IT8780F v0.3 102 IT8780F relative seek data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks wo 1 dir 0 0 1 1 1 1 command codes wo 0 0 0 0 0 hds dr1 dr0 command wo rcn execution head is stepped in or out a programmable number of tracks dumpreg data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command wo 0 0 0 0 1 1 1 0 command codes execution registers placed in fifo ro pcn-drive 0 ro pcn-drive 1 ro pcn-drive 2 ro pcn-drive 3 ro srt hut ro hlt nd ro sc/eot ro lock 0 dc3 dc2 dc1 dc0 gap wg ro 0 eis dfifo polld fifothr result ro pretrk lock data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command wo lock 0 0 1 0 1 0 0 command codes result ro 0 0 0 lock 0 0 0 0 version data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command wo 0 0 0 1 0 0 0 0 command codes result ro 1 0 0 1 0 0 0 0 enhanced controller
www.ite.com.tw IT8780F v0.3 103 functional description sense interrupt status data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command wo 0 0 0 0 1 0 0 0 command codes ro st0 result ro pcn status information at the end of each seek operation sense drive status data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command wo 0 0 0 0 0 1 0 0 command codes wo 0 0 0 0 0 hds dr1 dr0 result ro st3 status information about fdd specify data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks wo 0 0 0 0 0 0 1 1 command codes wo srt hut command wo hlt nd perpendicular mode data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks wo 0 0 0 1 0 0 1 0 command codes command wo ow 0 dc3 dc2 dc1 dc0 gap wg invalid data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command wo invalid codes invalid command codes (no-op: fdc goes into standby state) result ro st0 st0 = 80h
www.ite.com.tw IT8780F v0.3 104 IT8780F 9.6.11 data transfer commands all data transfer commands utilize the same parameter bytes (except for format a track command) and return the same result data bytes. the only difference between them is the five bits (bit 0 ? bit 4) of the first byte. 9.6.11.1 read data the read data command contains nine command bytes that place the fdc into the read data mode. each read operation is initialized by a read data command. the fdc locates the sector to be read by matching id address marks and id fields from the command with the information on the diskette. the fdc then transfers the data to the fifo. when the data from the given sector have been read, the read data command is completed and the sector address is automatically incremented by 1. the data from the next sector are read and transferred to the fifo in the same manner. such a continuous read function is called a "multi-sector read operation". if a tc or an implied tc (fifo overrun/underrun) is received, the fdc stops sending data but continues to read data from the current sector and checks the crc bytes until the end of the sector is reached and the read operation is completed. the sector size is determined by the n parameter value as calculated in the equation below: sector size = 2 (7+n value) bytes. the dtl parameter determines the number of bytes to be transferred. therefore, if n = 00h, setting the sector size to 128 and the dtl parameter value is less than this, the remaining bytes will be read and checked for crc errors by the fdc. if this occurs in a write operation, the remaining bytes will be filled with 0. if the sector size is not 128 (n > 00h), dtl should be set to ffh. in addition to performing multi-sector read operations, the fdc can also perform multi-track read operations. when the mt parameter is set, the fdc can read both sides of a disk automatically. the combination of n and mt parameter values determines the amount of data that can be transferred during either type of read operation. table 9-18 shows the maximum data transfer capacity and the final sector the fdc reads based on these parameters. table 9-18. effects of mt and n bits mt n maximum data transfer capacity final sector read from disk 0 1 256 x 26 = 6656 26 on side 0 or side 1 1 1 256 x 52 = 13312 26 on side 1 0 2 512 x 15 = 7680 15 on side 0 or side 1 1 2 512 x 30 = 15360 15 on side 1 0 3 1024 x 8 = 8192 8 on side 0 or side 1 1 3 1024 x16 =16384 16 on side 1
www.ite.com.tw IT8780F v0.3 105 functional description 9.6.11.2 read deleted data the read deleted data command is the same as the read data command, except that a deleted data address mark (as opposed to a data address mark) is read at the beginning of the data field. this command is typically used to mark a bad sector on a diskette. 9.6.11.3 read a track after receiving a pulse from the index# pin, the read a track command reads the entire data field from each sector of the track as a continuous block. if any id or data field crc error is found, the fdc continues to read data from the track and indicates the errors at the end. because the multi-track [and skip] operation[s] is [are] not allowed under this command, the mt and sk bits should be low (0) during the command execution. this command terminates normally when the number of sectors specified by eot has not been read. however, if no id address mark has been found by the second occurrence of the index pulse, the fdc will set the ic code in the st0 to 01 indicating an abnormal termination, and then finish the command. 9.6.11.4 write data the write data command contains nine command bytes that place the fdc into the write data mode. each write operation is initialized by a write data command. the fdc locates the sector to be written by reading id fields and matching the sector address from the command with the information on the diskette. then the fdc reads the data from the host via the fifo and writes the data into the sector?s data field. finally, the fdc computes the crc value, storing it in the crc field and increments the sector number (stored in the r parameter) by 1. the next data field is written into the next sector in the same manner. such a continuous write function is called a "multi-sector write operation". if a tc or an implied tc (fifo overrun/underrun) is received, the fdc stops writing data and fills the remaining data field with 0s. if a check of the crc value indicates an error in the sector id field, the fdc will set the ic code in the st0 to 01 and the de bit in the st1 to 1, indicating an abnormal termination, and then terminate the write data command. the maximum data transfer capacity and the dtl, n, and mt parameters are the same as in the read data command. 9.6.11.5 write deleted data the write deleted data command is the same as the write data command, except that a deleted data address mark (instead of a data address mark) is written at the beginning of the data field. this command is typically used to mark a bad sector on a diskette. 9.6.11.6 format a track the format a track command is used to format an entire track. initialized by an index pulse, it writes data to the gaps, address marks, id fields and data fields according to the density mode selected (fm or mfm). the gap and data field values are controlled by the host-specified values programmed into n, sc, gpl, and d during the command phase. the data field is filled with the data byte specified by d. the four data bytes per sector (c, h, r and n) needed to fill the id field are supplied by the host. the c, r, h and n values must be renewed for each new sector of a track. only the r parameter value must be changed when a sector is formatted allowing the disk to be formatted with non-sequential sector addresses. these steps are repeated until a new index pulse is received, at which point the format a track command is terminated.
www.ite.com.tw IT8780F v0.3 106 IT8780F 9.6.11.7 scan the scan command allows the data read from the disk to be compared with the data sent from the system. there are three scan commands: scan equal disk data = system data scan high or equal disk data system data scan low or equal disk data system data the scan command execution continues until the scan condition has been met, or when the eot has been reached, or if tc is asserted. read errors on the disk have the same error condition as the read data command. if the sk bit is set, sectors with deleted data address marks are ignored. if all sectors read are skipped, the command terminates with the d3 bit of the st2 being set. the result phase of the command is shown below: table 9-19. scan command result status register command d2 d3 condition 0 1 disk = system scan equal 1 0 disk system 0 1 disk = system 0 0 disk > system scan high or equal 1 0 disk < system 0 1 disk = system 0 0 disk < system scan low or equal 1 0 disk > system 9.6.11.8 verify the verify command is used to read logical sectors containing a normal data address mark from the selected drive without transferring the data to the host. this command acts like a read data command except that no data are transferred to the host. this command is designed for post-format or post write verification. data are read from the disk, as the controller checks for valid address marks in the address and data fields. the crc is computed and checked against the previously stored value. because no data are transferred to the host, the tc (terminal count of dma) cannot be used to terminate this command. an implicit tc will be issued to the fdc by setting the ec bit. this implicit tc will occur when the sc value has been decremented to 0. this command can also be terminated by clearing the ec bit and when the eot value is equal to the final sector to be checked.
www.ite.com.tw IT8780F v0.3 107 functional description table 9-20. verify command result mt ec sc/eot termination result 0 0 sc = dtl eot # sectors per side no error 0 0 sc = dtl eot > # sectors per side abnormal termination 0 1 sc # sectors remaining and eot # sectors per side no error 0 1 sc > # sectors remaining or eot > # sectors per side abnormal termination 1 0 sc = dtl eot > # sectors per side no error 1 0 sc = dtl eot > # sectors per side abnormal termination 1 1 sc # sectors remaining and eot # sectors per side no error 1 1 sc > # sectors remaining or eot > # sectors per side abnormal termination 9.6.12 control commands the control commands do not transfer any data. instead, these commands are used to monitor and manage the data transfer. three of the control commands generate an interrupt when read id, re-calibrate and seek are finished. it is strongly recommended that a sense interrupt status command be issued after these commands capture their valuable interrupt information. the re-calibrate, seek and specify commands do not return any result bytes. 9.6.12.1 read id the read id command is used to find the actual recording head position. it stores the first readable id field value into the fdc registers. if the fdc cannot find an id address mark by the time a second index pulse is received, an abnormal termination will be generated by setting the ic code in the st0 to 01.
www.ite.com.tw IT8780F v0.3 108 IT8780F 9.6.12.2 configure the configure command determines some special operation modes of the controller. it does not need to be issued if the default values of the controller meet the system requirements. eis: enable implied seeks. a seek operation is performed before a read, write, scan or verify command. 0 = disabled (default). 1 = enabled. dfifo: disable fifo. 0 = enabled. 1 = disabled (default). polld: disable polling of the drives. 0 = enabled (default). when enabled, a single interrupt is generated after a reset. 1 = disabled. fifothr: the fifo threshold in the execution phase of data transfer commands. they are programmable from 00 to 0f hex (1 byte to 16 bytes). defaults to 1 byte. pretrk: the precompensation start track number. they are programmable from track 0 to ff hex (track 0 to track 255). defaults to track 0. 9.6.12.3 re-calibrate the re-calibrate command retracts the fdc read/write head to the track 0 position, resetting the value of the pcn counter and checking the trk0# status. if trk0# is low, the dir# pin remains low and step pulses are issued. if trk0# is high, se [and ec bits] of the st0 are set high, and the command is terminated. when trk0# remains low for 79 step pulses, the re-calibrate command is terminated by setting se and ec bits of st0 to high. consequently, for disks that can accommodate more than 80 tracks, more than one re-calibrate command is required to retract the head to the physical track 0. the fdc is in a non-busy state during the execution phase of this command, which makes it possible to issue another re-calibrate command in parallel with the current command. on power-up, software must issue a re-calibrate command to properly initialize the fdc and drives attached. 9.6.12.4 seek the seek command controls the fdc read/write head movement from one track to another. the fdc compares the current head position, which is stored in pcn, with ncn values after each step pulse determines what direction move the head if required. the direction of movement is determined below: pcn < ncn ? step in: sets dir# signal to 1 and issues step pulses. pcn > ncn ? step out: sets dir# signal to 0 and issues step pulses. pcn = ncn ? terminate the command by setting the st0 se bit to 1. the impulse rate of step pulse is controlled by stepping rate time (srt) bit in the specify command. the fdc is in a non-busy state during the execution phase of this command, making it possible to issue another seek command in parallel with the current command.
www.ite.com.tw IT8780F v0.3 109 functional description 9.6.12.5 relative seek the relative seek command steps the selected drive in or out in a given number of steps. the dir bit is used to determine to step in or out. rcn (relative cylinder number) is used to determine how many tracks step the head in or out from the current track. after the step operation is completed, the controller generates an interrupt, but the command has no result phase. no other command except the sense interrupt status command should be issued while a relative seek command is in progress. 9.6.12.6 dumpreg the dumpreg command is designed for system run-time diagnostics, and application software development and debug. this command has one byte of command phase and 10 bytes of result phase, which return the values of parameters set in other commands. 9.6.12.7 lock the lock command allows the programmer to fully control the fifo parameters after a hardware reset. if the lock bit is set to 1, the parameters dfifo, fifothr, and pretrk in the configure command are not affected by a software reset. if the bit is set to 0, those parameters are set to default values after a software reset. 9.6.12.8 version the version command is used to determine the controller being used. in result phase, a value of 90 hex is returned in order to be compatible with the 82077. 9.6.12.9 sense interrupt status the sense interrupt status command resets the interrupt signal (irq) generated by the fdc, and identifies the cause of the interrupt via the ic code and se bit of the st0 as shown in table 9-21. it may be necessary to generate an interrupt when any of the following conditions occur: ? before any data transfer or read id command ? after seek or re-calibrate commands (no result phase exists) ? when a data transfer is required during an execution phase in the non-dma mode table 9-21. interrupt identification se ic code cause of interrupt 0 11 polling. 1 00 normal termination of seek or re-calibrate command. 1 01 abnormal termination of seek or re-calibrate command. 9.6.12.10 sense drive status the sense drive status command acquires drive status information. it has no execution phase.
www.ite.com.tw IT8780F v0.3 110 IT8780F 9.6.12.11 specify the specify command sets the initial values for the hut (head unload time), hlt (head load time), srt (step rate time), and nd (non-dma mode) parameters. the possible values for hut, srt and hlt are shown in table 9-22, table 9-23 and table 9-24 respectively. the fdc is operated in dma or non-dma mode based on the value specified by the nd parameters. table 9-22. hut values parameter 1 mbps 500 kbps 300 kbps 250 kbps 0 128 256 426 512 1 8 16 26.7 32 ? ? ? ? ? e 112 224 373 448 f 120 240 400 480 table 9-23. srt values parameter 1 mbps 500 kbps 300 kbps 250 kbps 0 8 16 26.7 32 1 7.5 15 25 30 ? ? ? ? ? e 1 2 3.33 4 f 0.5 1 1.67 2 table 9-24. hlt values parameter 1 mbps 500 kbps 300 kbps 250 kbps 00 128 256 426 512 01 1 2 3.33 4 02 2 4 6.7 8 ? ? ? ? ? 7e 126 252 420 504 7f 127 254 423 508
www.ite.com.tw IT8780F v0.3 111 functional description 9.6.12.12 perpendicular mode the perpendicular mode command is used to support the unique read/write/format commands of perpendicular recording disk drives (4 mbytes unformatted capacity). this command configures each of the four logical drives as a perpendicular or conventional disk drive via the dc3-dc0 bits, or with the gap and wg control bits. perpendicular recording drives operates in ?extra high density? mode at 1 mbps, and are downward compatible with 1.44 mbyte and 720 kbyte drives at 500 kbps (high density) and 250 kbps (double density) respectively. this command should be issued during the initialization of the floppy disk controller. then, when a drive is accessed for a format a track or write data command, the controller adjusts the format or write data parameters based on the data rate. if wg and gap are used (not set to 00), the operation of the fdc is based on the values of gap and wg. if wg and gap are set to 00, setting dcn to 1 will set drive n to the perpendicular mode. dc3-dc0 are unaffected by a software reset, but wg and gap are both cleared to 0 after a software reset. table 9-25. effects of gap and wg on format a track and write data commands gap wg mode length of gap2 format field portion of gap2 re-written by write data command 0 0 conventional 22 bytes 0 bytes 0 1 perpendicular (500 kbps) 22 bytes 19 bytes 1 0 reserved (conventional) 22 bytes 0 bytes 1 1 perpendicular (1 mbps) 41 bytes 38 bytes table 9-26. effects of drive mode and data rate on format a track and write data commands data rate drive mode length of gap2 format field portion of gap2 re-written by write data command 250/300/500 kbps conventional perpendicular 22 bytes 22 bytes 0 bytes 19 bytes 1 mbps conventional perpendicular 22 bytes 41 bytes 0 bytes 38 bytes 9.6.12.13 invalid the invalid command indicates when an undefined command has been sent to fdc. the fdc will set bit 6 and bit 7 in the main status register to 1 and terminate the command without issuing an interrupt. 9.6.13 dma transfers dma transfers are enabled by the specify command and are initiated by the fdc by activating the ldrq# cycle during a data transfer command. the fifo is enabled directly by asserting the lpc dma cycles. 9.6.14 low power mode when writing a 1 to bit 6 of dsr, the controller is set to low power mode immediately. all the clock sources including data separator, microcontroller and write precompensation unit will be gated. the fdc can be resumed from the low-power state in two ways: one is a software reset via the dor or dsr, and the other is a read or write to either the data register or main status register. the second method is more preferred since all internal register values are retained.
www.ite.com.tw IT8780F v0.3 112 IT8780F 9.7 serial port (uart) description the IT8780F incorporates two enhanced serial ports that perform serial to parallel conversion on received data, and parallel to serial conversion on transmitted data. each of the serial channels individually contains a programmable baud rate generator which is capable of dividing the input clock by a number ranging from 1 to 65535. the data rate of each serial port can also be programmed from 115.2k baud down to 50 baud. the character options are programmable for 1 start bit; 1, 1.5 or 2 stop bits; even, odd, stick or no parity; and privileged interrupts. table 9-27. serial channel registers register dlab* address read write data 0 base + 0h rbr (receiver buffer register) tbr (transmitter buffer register) control 0 x x x 1 1 base + 1h base + 2h base + 3h base + 4h base + 0h base + 1h ier (interrupt enable register) iir (interrupt identification register) lcr (line control register) mcr (modem control register) dll (divisor latch lsb) dlm (divisor latch msb) ier fcr (fifo control register) lcr mcr dll dlm status x x x base + 5h base + 6h base + 7h lsr (line status register) msr (modem status register) scr (scratch pad register) lsr msr scr * dlab is bit 7 of the line control register. 9.7.1 data registers the tbr and rbr individually hold from five to eight data bits. if the transmitted data are less than eight bits, it aligns to the lsb. either received or transmitted data are buffered by a shift register, and are latched first by a holding register. the bit 0 of any word is first received and transmitted. (1) receiver buffer register (rbr) (read only, address offset=0, dlab=0) this register receives and holds the incoming data. it contains a non-accessible shift register which converts the incoming serial data stream into a parallel 8-bit word. (2) transmitter buffer register (tbr) (write only, address offset=0, dlab=0) this register holds and transmits the data via a non-accessible shift register, and converts the outgoing parallel data into a serial stream before the data transmission.
www.ite.com.tw IT8780F v0.3 113 functional description 9.7.2 control registers: ier, iir, fcr, dll, dlm, lcr and mcr (1) interrupt enable register (ier) (read/write, address offset=1, dlab=0) the ier is used to enable (or disable) four active high interrupts which activate the interrupt outputs with its lower four bits: ier(0), ier(1), ier(2), and ier(3). table 9-28. interrupt enable register description bit default description 7-4 - reserved 3 0 enable modem status interrupt sets this bit high to enable the modem status interrupt when one of the modem status registers changes its bit status. 2 0 enable receiver line status interrupt sets this bit high to enable the receiver line status interrupt which is caused when overrun, parity, framing or break occurs. 1 0 enable transmitter holding register empty interrupt sets this bit high to enable the transmitter holding register empty interrupt. 0 0 enable received data available interrupt sets this bit high to enable the received data available interrupt and time-out interrupt in the fifo mode. (2) interrupt identification register (iir) (read only, address offset=2) this register facilitates the host cpu to determine interrupt priority and its source. the priority of four existing interrupt levels is listed below: 1. receiver line status (highest priority) 2. received data ready 3. transmitter holding register empty 4. modem status (lowest priority) when a privileged interrupt is pending and the type of interrupt is stored in the iir which is accessed by the host, the serial channel holds back all interrupts and indicates the pending interrupts with the highest priority to the host. any new interrupts will not be acknowledged until the host access is completed. the contents of the iir are described in the table on the next page.
www.ite.com.tw IT8780F v0.3 114 IT8780F table 9-29. interrupt identification register fifo mode interrupt identification register interrupt set and reset functions bit 3 bit 2 bit 1 bit 0 priority level interrupt type interrupt source interrupt reset control 0 x x 1 - none none - 0 1 1 0 first receiver line status oe, pe, fe, or bi read lsr 0 1 0 0 second received data available received data available read rbr or fifo drops below the trigger level 1 1 0 0 second character time-out indication no characters have been removed from or input to the rcvr fifo during the last 4 character times and there is at least 1 character in it during this time read rbr 0 0 1 0 third transmitter holding register empty transmitter holding register empty read iir if thre is the interrupt source write thr 0 0 0 0 fourth modem status cts#, dsr#, ri#, dcd# read msr note: x = not defined iir(7), iir(6): are set when fcr(0) = 1. iir(5), iir(4): always logic 0. iir(3): in non-fifo mode, this bit is a logic 0. in the fifo mode, this bit is set along with bit 2 when a time-out interrupt is pending. iir(2), iir(1): used to identify the highest priority interrupt pending. iir(0): used to indicate a pending interrupt in either a hard-wired prioritized or polled environment with a logic 0 state. in such a case, iir contents may be used as a pointer that points to the appropriate interrupt service routine.
www.ite.com.tw IT8780F v0.3 115 functional description (3) fifo control register (fcr) (write only, address offset=2) this register is used to enable, clear the fifo, and set the rcvr fifo trigger level. table 9-30. fifo control register description bit default description 7-6 - receiver trigger level select these bits set the trigger levels for the rcvr fifo interrupt. 5-4 0 reserved 3 0 this bit does not affect the serial channel operation. rxrdy and txrdy functions are not available on this chip. 2 0 transmitter fifo reset this self-clearing bit clears all contents of the xmit fifo and resets its related counter to 0 via a logic "1." 1 0 receiver fifo reset setting this self-clearing bit to a logic 1 clears all contents of the rcvr fifo and resets its related counter to 0 (except the shift register). 0 0 fifo enable xmit and rcvr fifos are enabled when this bit is set high. xmit and rcvr fifos are disabled and cleared respectively when this bit is cleared to low. this bit must be a logic 1 if the other bits of the fcr are written to, or they will not be properly programmed. when this register is switched to non-fifo mode, all its contents are cleared. table 9-31. receiver fifo trigger level encoding fcr (7) fcr (6) rcvr fifo trigger level 0 0 1 byte 0 1 4 bytes 1 0 8 bytes 1 1 14 bytes (4) divisor latches (dll, dlm) (read/write, address offset=0,1 dlab=0) two 8-bit divisor latches (dll and dlm) store the divisor values in a 16-bit binary format. they are loaded during the initialization to generate a desired baud rate. (5) baud rate generator (brg) each serial channel contains a programmable brg which can take any clock input (from dc to 8 mhz) to generate standard ansi/ccitt bit rates for the channel clocking with an external clock oscillator. the dll or dlm is a number of 16-bit format, providing the divisor range from 1 to 2 16 to obtain the desired baud rate. the output frequency is 16x data rate.
www.ite.com.tw IT8780F v0.3 116 IT8780F table 9-32. baud rates using (24 mhz 13) clock desired baud rate divisor used 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 1 (6) scratch pad register (read/write, address offset=7) this 8-bit register does not control the uart operation in any way. it is intended as a scratch pad register to be used by programmers to temporarily hold general purpose data. (7) line control register (lcr) (read/write, address offset=3) lcr controls the format of the data character and supplies the information of the serial line. its contents are described on the next page.
www.ite.com.tw IT8780F v0.3 117 functional description table 9-33. line control register description bit default description 7 0 divisor latch access bit (dlab) must be set to high to access the divisor latches of the baud rate generator during read or write operations. it must be set low to access the data registers (rbr and tbr) or the interrupt enable register. 6 0 set break forces the serial output (sout) to the spacing state (logic 0) by a logic 1, and this state will be preserved until a low level resetting lcr(6) enables the serial port to alert the terminal in a communication system. 5 0 stick parity when this bit and lcr(3) are high at the same time, the parity bit is transmitted, and then detected by receiver, in opposite state by lcr(4) to force the parity bit into a known state and to check the parity bit in a known state. 4 0 even parity select when parity is enabled (lcr(3) = 1), lcr(4) = 0 selects odd parity, and lcr(4) = 1 selects even parity. 3 0 parity enable a parity bit, located between the last data word bit and stop bit, will be generated or checked (transmit or receive data) when lcr(3) is high. 2 0 number of stop bits this bit specifies the number of stop bits in each serial character, as summarized in table 9-34. 1-0 00 word length select [1:0] 11: 8 bits 10: 7 bits 01: 6 bits 00: 5 bits table 9-34. stop bits number encoding lcr (2) word length no. of stop bits 0 - 1 1 5 bits 1.5 1 6 bits 2 1 7 bits 2 1 8 bits 2 note: the receiver will ignore all stop bits beyond the first, regardless of the number used in transmission.
www.ite.com.tw IT8780F v0.3 118 IT8780F (8) modem control register (mcr) (read/write, address offset=4) controls the interface by the modem or data set (or device emulating a modem). table 9-35. modem control register description bit default description 7-5 - reserved 4 0 internal loopback provides a loopback feature for diagnostic test of the serial channel when it is set high. serial output (sout) is set to the marking state shift register output loops back into the receiver shift register. all modem control inputs (cts#, dsr#, ri# and dcd#) are disconnected. the four modem control outputs (dtr#, rts#, out1 and out2) are internally connected to the four modem control inputs, and are forced to inactive high and the transmitted data are immediately received, allowing the processor to verify the transmit and receive data path of the serial channel. 3 0 out2 the output 2 bit enables the serial port interrupt output by a logic 1. 2 0 out1 this bit does not have an output pin and can only be read or written by the cpu. 1 0 request to send (rts) controls the request to send (rts#) which is in an inverse logic state with that of mcr(1). 0 0 data terminal ready (dtr) controls the data terminal ready (dtr#) which is in an inverse logic state with that of the mcr(0). 9.7.3 status registers: lsr and msr (1) line status register (lsr) (read/write, address offset=5) this register provides status indications and is usually the first register read by the cpu to determine the cause of an interrupt or to poll the status of each serial channel. the contents of the lsr are described below: table 9-36. line status register description bit default description 7 0 error in receiver fifo in 16450 mode, this bit is always 0. in the fifo mode, it sets high when there is at least one parity error, framing or break interrupt in the fifo. this bit is cleared when the cpu reads the lsr if there are no subsequent errors in the fifo. 6 1 transmitter empty this read only bit indicates that the transmitter holding register and transmitter shift register are both empty. otherwise, this bit is "0", and has the same function in the fifo mode.
www.ite.com.tw IT8780F v0.3 119 functional description table 9-36. line status register description [cont?d] bit default description 5 1 transmitter holding register empty transmitter holding register empty (thre). this read only bit indicates that the tbr is empty and is ready to accept a new character for transmission. it is set high when a character is transferred from the thr into the transmitter shift register, causing a priority 3 iir interrupt which is cleared by a read of iir. in the fifo mode, it is set when the xmit fifo is empty, and is cleared when at least one byte is written to the xmit fifo. 4 0 line break break interrupt (bi) status bit indicates that the last character received was a break character, (invalid but entire character), including parity and stop bits. this occurs when the received data input is held in the spacing (logic 0) for longer than a full word transmission time (start bit + data bits + parity + stop bit). when any of these error conditions is detected (lsr(1) to lsr(4)), a receiver line status interrupt (priority 1) will be generated in the iir, with the ier(2) previously enabled. 3 0 framing error framing error (fe) bit, a logic 1, indicates that the stop bit in the received character is not valid. it resets low when the cpu reads the contents of the lsr. 2 0 parity error parity error (pe) indicates by a logic 1 that the received data character does not have the correct even or odd parity, as selected by lcr(4). it will be reset to "0" whenever the lsr is read by the cpu. 1 0 overrun error overrun error (oe) bit indicates by a logic 1 that the rbr has been overwritten by the next character before it had been read by the cpu. in the fifo mode, the oe occurs when the fifo is full and the next character has been completely received by the shift register. it will be reset when the lsr is read by the cpu. 0 0 data ready a "1" indicates a character has been received by the rbr. a logic "0" indicates all the data in the rbr or the rcvr fifo have been read.
www.ite.com.tw IT8780F v0.3 120 IT8780F (2) modem status register (msr) (read/write, address offset=6) this 8-bit register indicates the current state of the control lines with modems or the peripheral devices in addition to this current state information. four of these eight bits msr(4)-msr(7) can provide the state change information when a modem control input changes state. it is reset low when the host reads the msr. table 9-37. modem status register description bit default description 7 0 data carrier detect data carrier detect - indicates the complement status of data carrier detect (dcd#) input. if mcr(4) = 1, msr(7) is equivalent to out2 of the mcr. 6 0 ring indicator ring indicator (ri#) - indicates the complement status to the ri# input. if mcr(4)=1, msr(6) is equivalent to out1 in the mcr. 5 0 data set ready data set ready (dsr#) - indicates that the modem is ready to provide received data to the serial channel receiver circuitry. if the serial channel is in the loop mode (mcr(4) = 1), msr(5) is equivalent to dtr# in the mcr. 4 0 clear to send clear to send (cts#) - indicates the complement of cts# input. when the serial channel is in the loop mode (mcr(4)=1), msr(5) is equivalent to rts# in the mcr. 3 0 delta data carrier detect indicates that the dcd# input state has been changed since the last time read by the host. 2 0 trailing edge ring indicator indicates that the ri input state to the serial channel has been changed from a low to high since the last time read by the host. the change to a logic ?1? does not activate the teri. 1 0 delta data set ready delta data set ready (ddsr) - a logic "1" indicates that the dsr# input state to the serial channel has been changed since the last time read by the host. 0 0 delta clear to send this bit indicates the cts# input to the chip has changed state since the last time the msr was read.
www.ite.com.tw IT8780F v0.3 121 functional description 9.7.4 reset the reset of the IT8780F should be held to an idle mode reset high for 500 ns until initialization, which causes the initialization of the transmitter and receiver internal clock counters. table 9-38. reset control of registers and pinout signals is shown below. table 9-38. reset control of registers and pinout signals register/signal reset control reset status interrupt enable register interrupt identification register fifo control register line control register modem control register line status register modem status register sout1, sout2 rts1#, rts2#, dtr1#, dtr2# irq of serial port reset reset reset reset reset reset reset reset reset reset all bits low bit 0 is high and bits 1-7 are low all bits low all bits low all bits low bits 5 and 6 are high, others are low bits 0-3 low, bits 4-7 input signals high high high impedance 9.7.5 programming each serial channel of the IT8780F is programmed by control registers, whose contents define the character length, number of stop bits, parity, baud rate and modem interface. although the control register can be written in any given order, the ier should be the last register written because it controls the interrupt enables. after the port is programmed, these registers can still be updated whenever the port is not transferring data. 9.7.6 software reset this approach allows the serial port returning to a completely known state without a system reset. this is achieved by writing the required data to the lcr, dll, dlm and mcr. the lsr and rbr must be read before interrupts are enabled to clear out any residual data or status bits that may be invalid for subsequent operations. 9.7.7 clock input operation the input frequency of the serial channel is 24 mhz 13, not exactly 1.8432 mhz.
www.ite.com.tw IT8780F v0.3 122 IT8780F 9.7.8 fifo interrupt mode operation (1) rcvr interrupt when setting fcr(0)=1 and ier(0)=1, the rcvr fifo and receiver interrupts are enabled. the rcvr interrupt occurs under the following conditions: the receive data available interrupt will be issued only if the fifo has reached its programmed trigger level. they will be cleared as soon as the fifo drops below its trigger level. the receiver line status interrupt has higher priority over the received data available interrupt. the time-out timer will be reset after receiving a new character or after the host reads the rcvr fifo whenever a time-out interrupt occurs. the timer will be reset when the host reads one character from the rcvr fifo. rcvr fifo time-out interrupt: by enabling the rcvr fifo and receiver interrupts, the rcvr fifo time-out interrupt will occur under the following conditions: the rcvr fifo time-out interrupt will occur only if there is at least one character in the fifo whenever the interval between the most recent received serial character and the most recent host read from the fifo is longer than four consecutive character times. the time-out timer will be reset after receiving a new character or after the host reads the rcvr fifo whenever a time-out interrupt occurs. the timer will be reset when the host reads one character from the rcvr fifo. (2) xmit interrupt by setting fcr(0) and ier(1) to high, the xmit fifo and transmitter interrupts are enabled, and the xmit interrupt occurs under the conditions described below: a. the transmitter interrupt occurs when the xmit fifo is empty, and it will be reset if the thr is written or the iir is read. b. the transmitter fifo empty indications will be delayed one character time minus the last stop bit time whenever the following condition occurs: thre = 1 and there have not been at least two bytes in the transmitter fifo at the same time since the last thre = 1. the transmitter interrupt after changing fcr(0) will be immediate, if it is enabled. once the first transmitter interrupt is enabled, the thre indication is delayed one character time minus the last stop bit time. the character time-out and rcvr fifo trigger level interrupts are in the same priority order as the received data available interrupt. the xmit fifo empty is in the same priority as the transmitter holding register empty interrupt. fifo polled mode operation [fcr(0)=1, and ier(0), ier(1), ier(2), ier(3) or all are 0]. either or both xmit and rcvr can be in this operation mode. the operation mode can be programmed by users and is responsible for checking the rcvr and xmit status via the lsr described below: lsr(7): rcvr fifo error indication. lsr(6): xmit fifo and shift register empty. lsr(5): the xmit fifo empty indication. lsr(4) - lsr(1): specify that errors have occurred. character error status is handled in the same way as in the interrupt mode. the iir is not affected since ier(2)=0. lsr(0): high whenever the rcvr fifo contains at least one byte. no trigger level is reached or time-out condition indicated in the fifo polled mode.
www.ite.com.tw IT8780F v0.3 123 functional description 9.8 smart card reader 9.8.1 features as an ifd (interface device) built in IT8780F, the smart card reader (scr) includes a standard uart (serial port 2 is set in scr mode) to control smart card interface handshaking and then performs data transfers, and can be connected to smart card socket directly. the smart card is capable of providing secured storage facilities for sensitive personal information such as private keys, account numbers, passwords, medical information, ?etc. then the scr can be used for a broad range of applications in gsm, id, pay tv, banking (refer to emv?96 spec.), ? and so forth. it also provides a smart card clock divider for those icc (integrated circuit card) without internal clocks. 9.8.2 operation the scr is a low-power consumption design. whenever the ifd is inactive, the clock divider will turn off internal clocks even when the clock of ifd controlling / monitoring state machine is turned off to save power consumption. also it could be waked up immediately when ic card is removed in case of emergency or when the fet control function is turned on/off. the vcc power of ic card interface is powered from an external fet to protect the smart card interface. also, the charge/discharge time for fet to reach 5v/0v is programmable, and fet performs automatically to meet iso 7816 activation and deactivation sequences. the uart?s modem control lines: dtr#, rts# and dcd# are used for controlling fet on/off, smart card reset signal and ic card insertion detection respectively. when an ic card is being inserted, it will switch the scrpres# (smart card present detect#) and then cause the dcd# signal to trigger an interrupt to the system. then in the smart card interrupt service routine, the driver can assert the dtr# signal to power on the external fet (scrpfet#) and the rts# signal to control the smart card reset signal (scrrst). in the mean time, IT8780F will generate a proper clock frequency to allow the ic card using default serial transfer baud rate to send back an atr (answer-to-reset) sequence. the interface signals are enabled after vcc reaches enough voltage level. then transfer protocol may be negotiated to promote more efficient transfers. in the same way, when the ic card is removed in case of emergency or when the icc processing is finished, the driver can de-assert the dtr# to turn off the fet power. but before the fet power-off and the reset, clock and data signals will be de-active, followed by a sufficient fet discharge time guaranteed to protect ic card and ifd. 9.8.3 connection of ifd to icc socket scrpres# scrpfet# scrrst scrclk scrio fet scr_ifd in IT8780F uart clock generator ifd vcc reset clock rfu rfu i/o vpp gnd ic card figure 9-7. smart card reader application
www.ite.com.tw IT8780F v0.3 124 IT8780F 9.8.4 baud rate relationship between uart and smart card interface to perform serial transfers correctly, the baud rate of uart must be set in ways similar to the icc card. ? formula (variation < 2%) smart card uart 24 mhz 13 16 * n baud rate = scrclk * d f n =divisor of uart, assigned by programming the dlm (divisor latch msb) and dll (divisor latch lsb). f =clock rate conversion factor, default = 372. d =bit rate adjustment factor, default is 1. scrclk duty cycle is 45%-55%. ? icc with internal clock icc may use built-in internal clock, then the baud rate is 9600 baud, just programming the divisor latch registers of uart in the IT8780F for scr ifd. ? icc without internal clock baud rate is scrclk/372 before negotiating, and scrclk is limited within 1 mhz - 5mhz. during the atr sequence, the default f value (clock rate conversion factor) is 372, and the default d value (bit rate adjustment factor) is 1. 9.8.5 waveform relationship scrclk scrio 9600 baud rate output 1 etu=372 scrclk (24 mhz/13)/12/16 (24 mhz/13)/12 16 baud clocks 1/9600 seconds figure 9-8. 9600 baud rate example 9.8.6 clock divider the scrclk is generated as the selection of scr_clksel1-0, which are determined in the s2 special configuration register 3 (ldn2_f2h). table 9-39. scrclk selections scr_clksel1-0 selections 00 stop 01 3.5 mhz 10 7.1 mhz 11 96 mhz / scr div96m note note: scr div96m is determined by s2 special configuration register 4 (ldn2_f4h).
www.ite.com.tw IT8780F v0.3 125 functional description 9.8.7 waveform example of activation/deactivation sequence scrpres# cardvcc sout scrclk scrpfet# scrrst dtr# rts# flow_clk scr_power-on interrupt enable : 1. scrrst = ~rts# 2. scrclk if scr_clksel1-0 is not 00b. scrio enable scrio atr, pts, xfer pts, tx activation sequence atr from icc with internal reset deactivation sequence interrupt if ic card emergency removed vcc charge time is 13/53/212 s figure 9-9. waveform example of ifd ? activation sequence refer to the waveform above. the scr ifd in the IT8780F will make sure that the ifd is in data receive mode (i.e. the sout from uart is high), and the rts# should be programmed to high. the scrclk is then enabled to output to the ic card (which means that the ic card can count scrclk clock numbers to start atr responses), the data transfer is then enabled, and the scrrst is the inverse logic state of rts#. also, the operation procedure guarantees the correct activation sequence even if the driver cannot program the scrclk and scrrst in the precise time points. in this way, the hardware meets the icc specification. ? atr for the ic card with its own internal reset, its atr begins within 400-40000 scrclk cycles. if no atr is detected, the smart card ifd driver can then program the rts# to low and cause the scrrst to high. for some types of ic cards without internal reset signals, it will check out the scrrst as active low reset, and begin its atr within 400-40000 scrclk cycles from the time point of scrrst rising edge. the IT8780F does not support the type of ic card that may send synchronous atrs. ? deactivation and pts structure whenever the ic card is removed or when the ifd driver intends to power off the scr interface, the ifd will enter the deactivation sequence. 9.8.8 atr and pts structure the contents of the atr (answer-to-reset) and pts (protocol-type-select) are defined in iso/iec 7816-x standards, which must be fully communicated by the icc resource manager, the icc service provider or the icc application software. after finalizing the coherent protocol, the scr ifd enters the normal transfer mode. since the scrio is the only data channel for both data transmit and receive as defined in the icc specification, the IT8780F can only support the half-duplex function. the scrrst can be resent when a data transfer error occurs, and then the ifd driver will select a safer, lower-speed protocol to perform the data transfers again.
www.ite.com.tw IT8780F v0.3 126 IT8780F 9.8.9 smart card operating sequence example insert n power up, clock y atr reset card n1 decoding atr more protocols pts request pts confirm change protocol transfer protocol error idle clock stop n y y y h/w reset emergency remove waiting for icc insertion interrupt by uart sense present# power up fet to 5v, then allow clock out and reset control, i/o in receive mode active level may differ icc responses to answer-to-reset within 400 - 40000 clo c cycles of scclk, if n1, then reset active high, if n2, the n deactive power down finish y n remove n2 driver translates the atr if no protocol is available, then treat as all default setting; if more protocols are available, the driver can select a suita transfer protocol ifd sends protocol-type-selection request, and intends to change xfer protocol if the icc accepts, then returns a confirm code both ifd and icc changed to new compromised protocol begin to xfer data for normal deactivation, the driver controls the ifd to ente r deactive sequence stop clock then power down fet if users remove the icc at any time
www.ite.com.tw IT8780F v0.3 127 functional description 9.9 parallel port the IT8780F incorporates one multi-mode high performance parallel port, which supports the ibm at, ps/2 compatible bi-directional standard parallel port (spp), the enhanced parallel port (epp) and the extended capabilities port (ecp). please refer to the IT8780F configuration registers and configuration description for information on enabling/disabling, changing the base address of the parallel port, and operation mode selection. table 9-40. parallel port connector in different modes host connector pin no. spp epp ecp 1 108 stb# write# nstrobe 2-9 109-116 pd0 - 7 pd0 - 7 pd0 - 7 10 103 ack# intr nack 11 102 busy wait# busy periphack(2) 12 101 pe (nu) (1) perror nackreverse(2) 13 100 slct (nu) (1) select 14 107 afd# dstb# nautofd hostack(2) 15 106 err# (nu) (1) nfault nperiphrequest(2) 16 105 init# (nu) (1) ninit nreverserequest(2) 17 104 slin# astb# nselectin note 1: nu: not used. note 2: fast mode. note 3: for more information, please refer to the ieee 1284 standard. 9.9.1 spp and epp modes table 9-41. address map and bit map for spp and epp modes register address i/o d0 d1 d2 d3 d4 d5 d6 d7 mode data port base 1+0h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 spp/epp status port base 1+1h ro tmout 1 1 err# slct pe ack# busy# spp/epp control port base 1+2h r/w stb afd init slin irqe pddi r 1 1 spp/epp epp address port base 1+3h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 epp epp data port0 base 1+4h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 epp epp data port1 base 1+5h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 epp epp data port2 base 1+6h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 epp epp data port3 base 1+7h r/w pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 epp note 1: the base address 1 depends on the logical device configuration registers of parallel port (0x60, 0x61).
www.ite.com.tw IT8780F v0.3 128 IT8780F (1) data port (base address 1 + 00h) this is a bi-directional 8-bit data port. the direction of data flow is determined by the bit 5 of the logic state of the control port register. it forwards directions when the bit is low and reverses directions when the bit is high. (2) status port (base address 1 + 01h) this is a read only register. writing to this register has no effects. the contents of this register are latched during an ior cycle. bit 7 - busy#: inverse of printer busy signal, a logic "0" means that the printer is busy and cannot accept another character. a logic "1" means that it is ready to accept the next character. bit 6 - ack#: printer acknowledge, a logic "0" means that the printer has received a character and is ready to accept another. a logic "1" means that it is still processing the last character. bit 5 - pe: paper end, a logic "1" indicates the paper end. bit 4 - slct: printer selected, a logic "1" means that the printer is on line. bit 3 - err#: printer error signal, a logic "0" means an error has been detected. bits 2, 1 - reserved: these bits are always "1" when read. bit 0 - tmout: this bit is valid only in epp mode and indicates that a 10-msec time-out has occurred in epp operation. a logic "0" means no time-out occurred and a logic ?1? means that a time-out error has been detected. this bit is cleared by an lreset# or by writing a logic ?1? to it. when the IT8780F is selected to non-epp mode (spp or ecp), this bit is always a logic "1" when read. (3) control port (base address 1 + 02h) this port provides all output signals to control the printer. the register can be read and written. bits 6, 7- reserved: these two bits are always "1" when read. bit 5 - pddir: data port direction control. this bit determines the direction of the data port register. set this bit "0" to output the data port to pd bus, and "1" to input from pd bus. bit 4 - irqe: interrupt request enable. setting this bit "1" enables the interrupt requests from the parallel port to the host. an interrupt request is generated by a "0" to "1" transition of the ack# signal. bit 3 - slin: inverse of slin# pin. setting this bit to "1" selects the printer. bit 2 - init: initiate printer. setting this bit to "0" initializes the printer. bit 1 - afd: inverse of the afd# pin. setting this bit to "1" causes the printer to automatically advance one line after each line is printed. bit 0 - stb: inverse of the stb# pin. this pin controls the data strobe signal to the printer. (4) epp address port (base address 1 + 03h) the epp address port is only available in the epp mode. when the host writes to this port, the contents of d0 -d7 are buffered and output to pd0 - pd7. the leading edge of iow (internal signal, active when lpc i/o write cycle is on this address) causes an epp address write cycle. when the host reads from this port, the contents of pd0 - pd7 are read. the leading edge of ior (internal signal, active when lpc i/o read cycle is on this address) causes an epp address read cycle. (5) epp data ports 0-3 (base address 1 + 04-07h) the epp data ports are only available in the epp mode. when the host writes to these ports, the contents of d0 - d7 are buffered and output to pd0 - pd7. the leading edge of iow (internal signal, active when lpc i/o write cycle is on this address) causes an epp data write cycle. when the host reads from these ports, the contents of pd0 - pd7 are read. the leading edge of ior (internal signal, active when lpc i/o read cycle is on this address) causes an epp data read cycle.
www.ite.com.tw IT8780F v0.3 129 functional description 9.9.2 epp mode operation when the parallel port of the IT8780F is set in the epp mode, the spp mode is also available. if no epp address/data port address is decoded (base address + 03h- 07h), the pd bus is in the spp mode, and the output signals such as stb#, afd#, init# and slin# are set by the spp control port. the direction of the data port is controlled by the bit 5 of the control port register. there is a 10-msec time required to prevent the system from lockup. the time has elapsed from the beginning of the iochrdy (internal signal: when active, the IT8780F will issue long wait in sync field) high (epp read/write cycle) to wait# being de-asserted. if a time-out occurs, the current epp read/write cycle is aborted and a logic "1" will be read in the bit 0 of the status port register. the host must write 0 to bits 0, 1, 3 of the control port register before any epp read/write cycle (epp spec.). the pins stb#, afd# and slin# are controlled by hardware for the hardware handshaking during epp read/write cycle. (1) epp address write 1. the host writes a byte to the epp address port (base address + 03h). the chip drives d0 - d7 onto pd0 - pd7. 2. the chip asserts write# (stb#) and astb# (slin#) after iow becomes active. 3. the peripheral de-asserts wait#, indicating that the chip may begin the termination of this cycle. then, the chip de-asserts astb#, latches the address from d0 - d7 to pd bus, allowing the host to complete the i/o write cycle. 4. the peripheral asserts wait#, indicating that it acknowledges the termination of the cycle. then, the chip de-asserts write to terminate the cycle. (2) epp address read 1. the host reads a byte from the epp address port. the chip drives pd bus to tri-state for the peripheral to drive. 2. the chip asserts astb# after ior becomes active. 3. the peripheral drives the pd bus valid and de-asserts wait#, indicating that the chip may begin the termination of this cycle. then, the chip de-asserts astb#, latches the address from pd bus to d0 -d7, allowing the host to complete the i/o read cycle. 4. the peripheral drives the pd bus to tri-state and then asserts wait#, indicating that it acknowledges the termination of the cycle. (3) epp data write 1. the host writes a byte to the epp data port (base address +04h - 07h). the chip drives d0- d7 onto pd0 -pd7. 2. the chip asserts write# (stb#) and dstb# (afd#) after iow becomes active. 3. the peripheral de-asserts wait#, indicating that the chip may begin the termination of this cycle. then, the chip de-asserts dstb#, latches the data from d0 - d7 to the pd bus, allowing the host to complete the i/o write cycle. 4. the peripheral asserts wait#, indicating that it acknowledges the termination of the cycle. then, the chip de-asserts write to terminate the cycle. (4) epp data read 1. the host reads a byte from the epp data port. the chip drives pd bus to tri-state for the peripheral to drive. 2. the chip asserts dstb# after ior becomes active. 3. the peripheral drives pd bus valid and de-asserts wait#, indicating that the chip may begin the termination of this cycle. then, the chip de-asserts dstb#, latches the data from pd bus to d0 - d7, allowing the host to complete the i/o read cycle. 4. the peripheral tri-states the pd bus and then asserts wait#, indicating that it acknowledges the termination of the cycle.
www.ite.com.tw IT8780F v0.3 130 IT8780F 9.9.3 ecp mode operation this mode is both software and hardware compatible with the existing parallel ports, allowing ecp to be used as a standard lpt port when the ecp mode is not required. it provides an automatic high-burst-bandwidth channel that supports dma or the ecp mode in both forward and reverse directions. a 16-byte fifo is implemented in both forward and reverse directions to smooth data flow and enhance the maximum bandwidth requirement allowed. the port supports automatic handshaking for the standard parallel port to improve compatibility and expedite the mode transfer. it also supports run-length encoded (rle) decompression in hardware. compression is accomplished by counting identical bytes and transmitting an rle byte that indicates how many times a byte has been repeated. the IT8780F does not support hardware rle compression. for a detailed description, please refer to "extended capabilities port protocol and isa interface standard". table 9-42. bit map of the ecp registers register d7 d6 d5 d4 d3 d2 d1 d0 data pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 ecpafifo addr/rle address or rle field dsr nbusy nack perror select nfault 1 1 1 dcr 1 1 pddir irqe selectin ninit autofd strobe cfifo parallel port data fifo ecpdfifo ecp data fifo tfifo test fifo cnfga 0 0 0 1 0 0 0 0 cnfgb 0 intrvalue 0 0 0 0 0 0 ecr mode nerrintren dmaen serviceintr full empty
www.ite.com.tw IT8780F v0.3 131 functional description (1) ecp register definitions table 9-43. ecp register definitions name address i/o ecp mode function data base 1 +000h r/w 000-001 data register ecpafifo base 1 +000h r/w 011 ecp fifo (address) dsr base 1 +001h r/w all status register dcr base 1 +002h r/w all control register cfifo base 2 +000h r/w 010 parallel port data fifo ecpdfifo base 2 +000h r/w 011 ecp fifo (data) tfifo base 2 +000h r/w 110 test fifo cnfga base 2 +000h ro 111 configuration register a cnfgb base 2 +001h r/w 111 configuration register b ecr base 2 +002h r/w all extended control register note 1: the base address 1 depends on the logical device configuration registers of parallel port (0x60, 0x61). note 2: the base address 2 depends on the logical device configuration registers of parallel port (0x62, 0x63). (2) ecp mode descriptions table 9-44. ecp mode descriptions mode description 000 standard parallel port mode 001 ps/2 parallel port mode 010 parallel port fifo mode 011 ecp parallel port mode 110 test mode 111 configuration mode note: please refer to the ecp register description on pages 137-138 for a detailed description of the mode selection.
www.ite.com.tw IT8780F v0.3 132 IT8780F (3) ecp pin descriptions table 9-45. ecp pin descriptions name attribute description nstrobe (hostclk) o used for handshaking with busy to write data and addresses into the peripheral device. pd0-pd7 i/o address or data or rle data. nack (periphclk) i used for handshaking with nautofd to transfer data from the peripheral device to the host. busy (periphack) i the peripheral uses this signal for flow control in the forward direction (handshaking with nstrobe). in the reverse direction, this signal is used to determine whether a command or data information is present on pd0-pd7. perror (nackreverse) i used to acknowledge ninit from the peripheral which drives this signal low, allowing the host to drive the pd bus. select i printer on-line indication. nautofd (hostack) o in the reverse direction, it is used for handshaking between the nack and the host. when it is asserted, a peripheral data byte is requested. in the forward direction, this signal is used to determine whether a command or data information is present on pd0 - pd7. nfault (nperiphrequest) i in the forward direction (only), the peripheral is allowed (but not required) to assert this signal (low) to request a reverse transfer while in ecp mode. the signal provides a mechanism for peer-to-peer communication. it is typically used to generate an interrupt to host, which has the ultimate control over the transfer direction. ninit (nreverserequest) o the host may drive this signal low to place the pd bus in the reverse direction. in the ecp mode, the peripheral is permitted to drive the pd bus when ninit is low, and nselectin is high. nselectin (1284 active) o always inactive (high) in the ecp mode. (4) data port (base 1+00h, modes 000 and 001) its contents will be cleared by a reset. in a write operation, the contents of the lpc data fields are latched by the data register. the contents are then sent without being inverted to pd0-pd7. in a read operation, the contents of data ports are read and sent to the host. (5) ecpafifo port (address/rle) (base 1 +00h, mode 011) any data byte written to this port are placed in the fifo and tagged as an ecp address/rle. the hardware then automatically sends this data to the peripheral. operation of this port is valid only in the forward direction (dcr(5)=0). (6) device status register (dsr) (base 1 +01h, mode all) bits 0, 1 and 2 of this register are not implemented. these bit states are remained at high in a read operation of the printer status register. dsr(7): this bit is the inverted level of the busy input. dsr(6): this bit is the state of the nack input. dsr(5): this bit is the state of the perror input. dsr(4): this bit is the state of the select input. dsr(3): this bit is the state of the nfault input. dsr(2)-dsr(0): these bits are always 1.
www.ite.com.tw IT8780F v0.3 133 functional description (7) device control register (dcr) (base 1+02h, mode all) bits 6 and 7 of this register have no function. they are set high during the read operation, and cannot be written. contents in bits 0-5 are initialized to 0 when the reset pin is active. dcr(7)-dcr(6): these two bits are always high. dcr(5): except in the modes 000 and 010, setting this bit low means that the pd bus is in output operation; on the contrary, setting it high means that the pd bus is in input operation. this bit will be forced to low in mode 000. dcr(4): setting this bit high enables the interrupt request from peripheral to the host due to a rising edge of the nack input. dcr(3): it is inverted and output to selectin. dcr(2): it is output to ninit without inversion. dcr(1): it is inverted and output to nautofd. dcr(0): it is inverted and output to nstrobe. (8) parallel port data fifo (cfifo) (base 2+00h, mode 010) bytes written or dma transferred from the host to this fifo are sent by a hardware handshaking to the peripheral according to the standard parallel port protocol. this operation is only defined for the forward direction. (9) ecp data fifo (ecpdfifo) (base 2+00h, mode 011) when the direction bit dcr(5) is 0, bytes written or dma transferred from the host to this fifo are sent by hardware handshaking to the peripheral according to the ecp parallel port protocol. when dcr(5) is 1, data bytes from the peripheral to this fifo are read in an automatic hardware handshaking. the host can receive these bytes by performing read operations or dma transfers from this fifo. (10) test fifo (tfifo) (base 2+00h, mode 110) the host may operate read/write or dma transfers to this fifo in any directions. data in this fifo will be displayed on the pd bus without using hardware protocol handshaking. the tfifo will not accept new data after it is full. making a read from an empty tfifo causes the last data byte to return. (11) configuration register a (cnfga) (base 2+00h, mode 111) this read only register indicates to the system that interrupts are isa-pulses compatible. this is an 8-bit implementation by returning a 10h. (12) configuration register b (cnfgb) (base 2+01h, mode 111) this register is read only . cnfgb(7): a logic ?0? read indicates that the chip does not support hardware rle compression. cnfgb(6): reserved. cnfgb(5)-cnfg(3): a value 000 read indicates that the interrupt must be selected with jumpers. cnfgb(2)-cnfg(0): a value 000 read indicates that the dma channel is jumpered 8-bit dma.
www.ite.com.tw IT8780F v0.3 134 IT8780F (13) extended control register (ecr) (base 2+02h, mode all) ecp function control register. ecr(7)-ecr(5): these bits are used for read/write and mode selection. table 9-46. extended control register (ecr) mode and description ecr mode and description 000 standard parallel port mode. the fifo is reset and the direction bit dcr(5) is always 0 (forward direction) in this mode. 001 ps/2 parallel port mode. it is similar to the spp mode, except that the dcr(5) is read/write . when dcr(5) is 1, the pd bus is tri-state. reading the data port returns the value on the pd bus instead of the value of the data register. 010 parallel port data fifo mode. this mode is similar to the 000 mode, except that the host writes or dma transfers the data bytes to the fifo. the fifo data are then transmitted to the peripheral using the standard parallel port protocol automatically. this mode is only valid in the forward direction (dcr(5)=0). 011 ecp parallel port mode. in the forward direction, bytes placed into the ecpdfifo and ecpafifo are placed in a single fifo and automatically transmitted to the peripheral under the ecp protocol. in the reverse direction, bytes are transmitted to the ecpdfifo from the ecp port. 100, 101 reserved, not defined. 110 test mode. in this mode, the fifo may be read from or written to, but it cannot be sent to the peripheral. 111 configuration mode. in this mode, the cnfga and cnfgb registers are accessible at 0x400 and 0x401. ecr(4): nerrintren, read/write, valid in ecp(011) mode 1: disables the interrupt generated on the asserting edge of the nfault input. 0: enables the interrupt pulse on the asserting edge of the nfault. an interrupt pulse will be generated if nfault is asserted, or if this bit is written from 1 to 0 in the low-level nfault. ecr(3): dmaen, read/write 1: enables dma. dma starts when serviceintr (ecr(2)) is 0. 0: disables dma unconditionally. ecr(2): serviceintr, read/write 1: disables dma and all service interrupts. 0: enables the service interrupts. this bit will be set to ?1? by hardware when one of the three service interrupts has occurred. writing ?1? to this bit will not generate an interrupt. case 1: dmaen=1 during dma, this bit is set to 1 (a service interrupt generated) if the terminal count is reached. case 2: dmaen=0, dcr(5)=0 this bit is set to 1 (a service interrupt generated) whenever there are writeintrthreshold or more bytes space free in the fifo. case 3: dmaen=0, dcr(5)=1 this bit is set to 1 (a service interrupt generated) whenever there are readintrthreshold or more valid bytes to be read from the fifo.
www.ite.com.tw IT8780F v0.3 135 functional description ecr(1): full, read only 1: the fifo is full and cannot accept another byte. 0: the fifo has at least 1 free data byte space. ecr(0): empty, read only 1: the fifo is empty. 0: the fifo contains at least 1 data byte. (14) mode switching operation in programmed i/o control (mode 000 or 001), p1284 negotiation and all other tasks that happen before data transmission are software-controlled. setting mode to 011 or 010 will cause the hardware to perform an automatic control-line handshaking, transferring information between the fifo and the ecp port. from the mode 000 or 001, any other mode may be immediately switched to any other mode. to change direction, the mode must first be set to 001. in the extended forward mode, the fifo must be cleared and all the signals must be de-asserted before returning to mode 000 or 001. in ecp reverse mode, all data must be read from the fifo before returning to mode 000 or 001. usually, unneeded data are accumulated during ecp reverse handshaking, when the mode is changed during a data transfer. in such conditions, nautofd will be de-asserted regardless of the transfer state. to avoid bugs during handshaking signals, these guidelines must be followed. (15) software operation (ecp) before the ecp operation can begin, it is first necessary for the host to switch the mode to 000 in order to negotiate with the parallel port. during this process, the host determines whether the peripheral supports the ecp protocol. after this negotiation is completed, the mode is set to 011 (ecp). to enable the drivers, the direction must be set to 0. both strobe and autofd are set to 0, causing nstrobe and nautofd signals to be de-asserted. all fifo data transfers are pword wide and pword aligned. permitted only in the forward direction, address/rle transfers are byte-wide. the ecp address/rle bytes may be automatically sent by writing to the ecpafifo. similarly, data pwords may be automatically sent via the ecpdfifo. to change directions, the host switches mode to 001. it then negotiates either the forward or reverse channel, sets the direction to 1 or 0, and finally switches mode to 001. if the direction is set to 1, the hardware performs the handshaking for each ecp data byte read, then tries to fill the fifo. at this time, pwords may be read from the ecpdfifo while it retains data. it is also possible to perform the ecp transfers by handshaking with individual bytes under programmed control in mode = 001, or 000, even though this is a comparatively time- consuming approach.
www.ite.com.tw IT8780F v0.3 136 IT8780F (16) hardware operation (dma) the standard pc dma protocol (through ldrq#) is followed. as in the programmed i/o case, software sets the direction and state. next, the desired count and memory addresses are programmed into dma controller. the dmaen is set to 1, and the serviceintr is set to 0. to complete the process, the dma channel with the dma controller is unmasked. the contents in the fifo are emptied or filled by dma using the right mode and direction. dma is always transferred to or from the fifo located at 0 x 400. by generating an interrupt and asserting a serviceintr, dma is disabled when the dma controller reaches the terminal count. by not asserting ldrq# for more than 32 consecutive dma cycles, blocking of refresh requests is eliminated. when it is necessary to disable a dma while performing a transfer, the host dma controller is disabled, serviceintr is then set to 1, and dmaen is next set to 0. if the contents in fifo are empty or full, the dma will start again. this is first done by enabling the host dma controller, and then setting dmaen to 1. finally, serviceintr is set to 0. upon completion of a dma transfer in the forward direction, the software program must wait until the contents in fifo are empty and the busy line is low, ensuring that all data successfully reach the peripheral device. (17) interrupts it is necessary to generate an interrupt when any of the following states are reached. 1. serviceintr = 0, dmaen = 0, direction = 0, and the number of pwords in the fifo is greater than or equal to writeintrthreshold. 2. serviceintr = 0, dmaen = 0, direction = 1, and the number of pwords in the fifo is greater than or equal to readintrthreshold. 3. serviceintr = 0, dmaen = 1, and dma reaches the terminal count. 4. nerrintren = 0 and nfault goes from high to low or when nerrintren is set from 1 to 0 and nfault is asserted. 5. ackinten = 1. in current implementations of using existing parallel ports, the interrupt generated may be either edge or level trigger type. (18) interrupt driven programmed i/o it is also possible to use an interrupt-driven programmed i/o to execute either ecp or parallel port fifos. an interrupt will occur in the forward direction when serviceintr is 0 and the number of free pwords in the fifo is equal to or greater than writeintrthreshold. if either of these conditions is not met, it may be filled with writeintrthreshold pwords. an interrupt will occur in the reverse direction when serviceintr is 0 and the number of available pwords in the fifo is equal to readintrthreshold. if it is full, the fifo can be completely emptied in a single burst. if it is not full, only a number of pwords equal to readintrthreshold may be read from the fifo in a single burst. in the test mode, software can determine the values of writeintrthreshold, readintrthreshold, and fifo depth while accessing the fifo. any pc lpc bus implementation that is adjusted to expedite dma or i/o transfer must ensure that the bandwidth on the isa is maintained on the interface. although the lpc (even pci) bus of pc cannot be directly controlled, the interface bandwidth of ecp port can be constrained to perform at the optimum speed.
www.ite.com.tw IT8780F v0.3 137 functional description (19) standard parallel port in the forward direction with dma, the standard parallel port is run at or close to the permitted peak bandwidth of 500 kb/sec. the state machine does not examine nack, but just begins the next dma based on the busy signal. 9.10 keyboard controller (kbc) the keyboard controller is implemented using an 8-bit microcontroller that is capable of executing the 8042 instruction set. for general information, please refer to the description of the 8042 in the 8-bit controller handbook. in addition, the microcontroller can enter power-down mode by executing two types of power-down instructions. the 8-bit microcontroller has 256 bytes of ram for data memory and 2 kbytes of rom for the program storage. the rom codes may come from various vendors (or users), and are programmed during the manufacturing process. to assist in developing rom codes, the keyboard controller has an external access mode. in the external access mode, the internal rom is disabled and the instructions executed by the microcontroller come from an externally connected rom. keyboard controller krst* kclk kdat mclk mdat gatea20 kirq mirq t0 p26 p10 p27 t1 p23 p11 p22 p24 p25 p20 p21 figure 9-10. keyboard and mouse interface
www.ite.com.tw IT8780F v0.3 138 IT8780F 9.10.1 host interface the keyboard controller interfaces with the system through the 8042 style host interface. table 9-47 shows how the interface decodes the control signals. table 9-47. data register read/write controls host address note r/w* function 60h ro read data 60h wo write data, (clear f1) 64h ro read status 64h wo write command, (set f1) note: these are the default values of the ldn5, 60h and 61h (data); ldn5, 62h and 63h (command). all these registers are programmable. read data: this is an 8-bit read only register. when read, the kirq output is cleared and obf flag in the status register is cleared. write data: this is an 8-bit write only register. when written, the f1 flag of the status register is cleared and the ibf bit is set. read status: this is an 8-bit read only register. refer to the description of the status register for more information. write command: this is an 8-bit write only register. when written, both f1 and ibf flags of the status register are set. 9.10.2 data registers and status register the keyboard controller provides two data registers: one is dbin for data input, and the other is dbout for data output. each of the data registers is 8-bit wide. a write (microcontroller) to the dbout will load keyboard data read buffer, set obf flag and set the kirq output. a read (microcontroller) of the dbin will read the data from the keyboard data or command write buffer and clear the ibf flag. the status register holds information concerning the status of the data registers, the internal flags, and some user-defined status bits. please refer to table 9-48. the bit 0 obf is set to ?1? when the microcontroller writes data into dbout, and is cleared when the system initiates a data read operation. the bit 1 ibf is set to ?1? when the system initiates a write operation, and is cleared when the microcontroller executes an ?in a, dbb? instruction. the f0 and f1 flags can be set or reset when the microcontroller executes the clear and complement flag instructions. f1 also holds the system write information when the system performs the write operations. table 9-48. status register 7 6 5 4 3 2 1 0 st7 st6 st5 st4 f1 f0 ibf obf
www.ite.com.tw IT8780F v0.3 139 functional description 9.10.3 keyboard and mouse interface kclk is the keyboard clock pin. its output is the inversion of pin p26 of the microcontroller, and the input of kclk is connected to the t0 pin of the microcontroller. kdat is the keyboard data pin; its output is the inversion of pin p27 of the microcontroller, and the input of kdat is connected to the p10 of the microcontroller. mclk is the mouse clock pin; its output is the inversion of pin p23 of the microcontroller, and the input of mclk is connected to the t1 pin of the microcontroller. mdat is the mouse data pin; its output is the inversion of pin p22 of the microcontroller, and the input of mdat is connected to the p11 of the microcontroller. krst# is pin p20 of the microcontroller. gatea20 is the pin p21 of the microcontroller. these two pins are used as software controlled or user defined outputs. external pull-ups may be required for these pins. 9.10.4 kirq and mirq kirq is the interrupt request for keyboard (default irq1), and mirq is the interrupt request for mouse (default irq12). kirq is internally connected to p24 pin of the microcontroller, and mirq is internally connected to pin p25 of the microcontroller.
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www.ite.com.tw IT8780F v0.3 141 dc electrical characteristics 10. dc electrical characteristics absolute maximum ratings* applied voltage...................................-0.3v to 4.6v input voltage (vi) ............................. -0.3v to 5.25v output voltage (vo) ............... -0.3v to vcc + 0.3v operation temperature (topt).............0 c to +70 c storage temperature .................... -55 c to +125 c power dissipation ...................................... 200mw *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics (vcc = 3.3v 5%, ta = 0 c to + 70 c) symbol parameter min. typ. max. unit conditions do8 buffer v ol low output voltage 0.4 v i ol = 8 ma v oh high output voltage 2.4 v i oh = -8 ma dod8 buffer v ol low output voltage 0.4 v i ol = 8 ma do16 buffer v ol low output voltage 0.4 v i ol = 16 ma v oh high output voltage 2.4 v i oh = -16 ma do 4/24 buffer v ol low output voltage 0.4 v i ol = 24 ma v oh high output voltage 2.4 v i oh = -4 ma do 16/24 buffer v ol low output voltage 0.4 v i ol = 24 ma v oh high output voltage 2.4 v i oh = -16 ma dio8 type buffer v ol low output voltage 0.4 v i ol = 8 ma v oh high output voltage 2.4 v i oh = -8 ma v il low input voltage 0.8 v v ih high input voltage 2.2 v i il low input leakage 10 a v in = 0 i ih high input leakage -10 a v in = vcc i oz 3-state leakage 20 a diod8 type buffer v ol low output voltage 0.4 v i ol = 8 ma v il low input voltage 0.8 v v ih high input voltage 2.2 v i il low input leakage 10 a v in = 0 i ih high input leakage -10 a v in = vcc i oz 3-state leakage 20 a
www.ite.com.tw IT8780F v0.3 142 IT8780F dc electrical characteristics (vcc = 5v 5%, ta = 0 c to + 70 c) [cont?d] symbol parameter min. typ. max. unit conditions dio16 type buffer v ol low output voltage 0.4 v i ol = 16 ma v oh high output voltage 2.4 v i oh = -16 ma v il low input voltage 0.8 v v ih high input voltage 2.2 v i il low input leakage 10 a v in = 0 i ih high input leakage -10 a v in = vcc i oz 3-state leakage 20 a diod16 type buffer v ol low output voltage 0.4 v i ol = 16 ma v il low input voltage 0.8 v v ih high input voltage 2.2 v i il low input leakage 10 a v in = 0 i ih high input leakage -10 a v in = vcc i oz 3-state leakage 20 a dio 16/24 type buffer v ol low output voltage 0.4 v i ol = 24 ma v oh high output voltage 2.4 v i oh = -16 ma v il low input voltage 0.8 v v ih high input voltage 2.2 v i il low input leakage 10 a v in = 0 i ih high input leakage -10 a v in = vcc i oz 3-state leakage 20 a di type buffer v il low input voltage 0.8 v v ih high input voltage 2.2 v i il low input leakage 10 a v in = 0 i ih high input leakage -10 a v in = vcc
www.ite.com.tw IT8780F v0.3 143 ac characteristics 11. ac characteristics (vcc = 5v 5%, ta = 0 c to + 70 c) 11.1 clock input timings symbol parameter min. typ. max. unit t 1 clock high pulse width when clkin=48 mhz 1 8 nsec t 2 clock low pulse width when clkin=48 mhz 1 8 nsec t 3 clock period when clkin=48 mhz 1 20 21 22 nsec t 4 clock high pulse width when clkin=24 mhz 1 18 nsec t 5 clock low pulse width when clkin=24 mhz 1 18 nsec t 6 clock period when clkin=24 mhz 1 40 42 44 nsec 1. not tested. guaranteed by design. t 1 , t 4 t 2 ,t 5 t 3 ,t 6 0.8v 2.2v 11.2 lclk (pciclk) and lreset# timings symbol parameter min. typ. max. unit t 1 lclk cycle time 28 nsec t 2 lclk high time 11 nsec t 3 lclk low time 11 nsec t 4 lreset# low pulse width 1.5 sec t 2 t 3 t 1 0.2vcc 0.6vcc 0.4vcc p-to-p (minimum)
www.ite.com.tw IT8780F v0.3 144 IT8780F 11.3 lpc and serirq timings symbol parameter min. typ. max. unit t 1 float to active delay 3 nsec t 2 output valid delay 12 nsec t 3 active to float delay 6 nsec t 4 input setup time 9 nsec t 5 input hold time 3 nsec t 2 t 1 t 3 lpc signals/ serirq (output) lclk lpc signals/ serirq (input) input valid t 5 t 4
www.ite.com.tw IT8780F v0.3 145 ac characteristics 11.4 serial port, askir, sir and consumer remote control timings symbol parameter conditions min. max. unit transmitter t btn ? 25 note1 t btn + 25 nsec t 1 single bit time in serial port and askir receiver t btn ? 2% t btn + 2% nsec transmitter 950 1050 nsec t 2 modulation signal pulse width in askir receiver 500 nsec transmitter 1975 2025 nsec t 3 modulation signal period in askir receiver 2000x(23/24) 2000x(25/24) nsec transmitter, variable (3/16) x t btn ? 25 (3/16) x t btn + 25 nsec transmitter, fixed 1.48 1.78 sec t 4 sir signal pulse width receiver 1 sec note 1: t btn is the nominal bit time in serial port, askir, and sir. it is determined by the setting on the baud rate divisor registers. serial port sir sharp-ir consumer remote control t 1 t 2 t 3 t 4 11.5 modem control timings symbol parameter min. typ. max. unit t 1 float to active delay 40 nsec cts1#, dsr1#, dcd1#, cts2#, dsr2#, dcd2# interrupt (internal signal) ri1#, ri2# t 1 (read msr) (read msr) t 1 t 1
www.ite.com.tw IT8780F v0.3 146 IT8780F 11.6 floppy disk drive timings symbol parameter min. typ. max. unit t 1 dir# active to step# low 4x t mclk note1 nsec t 2 step# active time (low) 24x t mclk nsec t 3 dir# hold time after step# t srt note2 msec t 4 step# cycle time t srt msec t 5 index# low pulse width 2x t mclk nsec t 6 rdata# low pulse width 40 nsec t 7 wdata# low pulse width 1x t mclk nsec note 1: t mclk is the cycle of main clock for the microcontroller of fdc. t mclk =8m/ 4m/ 2.4m/ 2m for 1m/ 500k/ 300k/ 250 kbps transfer rates respectively. note 2: t srt is the cycle of the step rate time. please refer to the functional description of the specify command of the fdc. dir# step# index# t 1 t 2 t 3 t 4 t 5 rdata# wdata# t 6 t 7
www.ite.com.tw IT8780F v0.3 147 ac characteristics 11.7 epp address or data write cycle timings symbol parameter min. typ. max. unit t 1 write# asserted to pd[7:0] valid 50 nsec t 2 astb# or dstb# asserted to wait# de-asserted 0 10 nsec t 3 wait# de-asserted to astb# or dstb# de-asserted 65 135 nsec t 4 astb# or dstb# de-asserted to wait# asserted 0 nsec t 5 wait# asserted to write# de-asserted 65 nsec t 6 pd[7:0] invalid after write# de-asserted 0 nsec write# astb# dstb# wait# pd[ 7:0 ] t 1 t 2 t 3 t 4 t 5 t 6
www.ite.com.tw IT8780F v0.3 148 IT8780F 11.8 epp address or data read cycle timings symbol parameter min. typ. max. unit t 1 astb# or dstb# asserted to wait# de-asserted 10 nsec t 2 astb# or dstb# asserted to pd[7:0] hi-z 0 nsec t 3 pd[7:0] valid to wait# de-asserted 0 nsec t 4 wait# de-asserted to astb# or dstb# de-asserted 65 135 nsec t 5 astb# or dstb# de-asserted to wait# asserted 0 nsec t 6 pd[7:0] invalid after astb# or dstb# de-asserted 20 nsec write# astb# dstb# wait# pd[ 7:0 ] t 1 t 2 t 3 t 4 t 5 t 6 11.9 ecp parallel port forward timings symbol parameter min. typ. max. unit t 1 pd[7:0] and nautofd valid to nstrobe asserted 50 nsec t 2 nstrobe asserted to busy asserted 0 nsec t 3 busy asserted to nstrobe de-asserted 70 170 nsec t 4 nstrobe de-asserted to busy de-asserted 0 nsec t 5 busy de-asserted to pd[7:0] and nautofd changed 80 180 nsec t 6 busy de-asserted to nstrobe asserted 70 170 nsec pd[7:0], nautofd nstrobe busy t 1 t 2 t 3 t 4 t 5 t 6
www.ite.com.tw IT8780F v0.3 149 ac characteristics 11.10 ecp parallel port backward timings symbol parameter min. typ. max. unit t 1 pd[7:0] valid to nack asserted 0 nsec t 2 nack asserted to nautofd asserted 70 170 nsec t 3 nautofd asserted to nack de-asserted 0 nsec t 4 nack de-asserted to nautofd de-asserted 70 170 nsec t 5 nautofd de-asserted to pd[7:0] changed 0 nsec t 6 nautofd de-asserted to nack asserted 0 nsec pd[7:0] nack nautofd t 1 t 2 t 3 t 4 t 5 t 6
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www.ite.com.tw IT8780F v0.3 151 package information 12. package information qfp 128l outline dimensions unit: inches/mm 39 64 d e a a 2 a 1 102 65 103 128 38 detail "a" 1 see detail "f" seating plane e 1 b d 1 e detail "a" d y 0.10 b base metal c with plating l 1 detail "f" l gage plane y dimension in inch dimension in mm symbol min. nom. max. min. nom. max. a - - 0.134 - - 3.40 a 1 0.010 - - 0.25 - - a 2 0.107 0.112 0.117 2.73 2.85 2.97 b 0.007 0.009 0.011 0.17 0.22 0.27 c 0.004 - 0.008 0.09 - 0.20 d 0.906 0.913 0.921 23.00 23.20 23.40 d 1 0.783 0.787 0.791 19.90 20.00 20.10 e 0.669 0.677 0.685 17.00 17.20 17.40 e 1 0.547 0.551 0.555 13.90 14.00 14.10 0.020 bsc 0.5 bsc l 0.029 0.035 0.041 0.73 0.88 1.03 l 1 0.063 bsc 1.60 bsc y - - 0.004 - - 0.10 0 - 7 0 - 7 notes: 1. dimensions d 1 and e 1 do not include mold protrusion, but mold mismatch is included. 2. dimension b does not include dambar protrusion. 3. controlling dimension: millimeter. e
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www.ite.com.tw IT8780F v0.3 153 ordering information 13. ordering information part no. package IT8780F 128 qfp

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